From 39c0b0356ccbae68b6763a1166ccf5e94d3ca4af Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 20 Jul 2023 15:44:18 +0200 Subject: [PATCH] bench/uartbone: Update with LiteX change. --- bench/arty.py | 2 +- bench/genesys2.py | 2 +- bench/kc705.py | 2 +- bench/kcu105.py | 2 +- bench/xcu1525.py | 2 +- litedram/phy/rpc/arty.py | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index 4b11865..5c6a3e7 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -95,7 +95,7 @@ class BenchSoC(SoCCore): # UARTBone --------------------------------------------------------------------------------- if uart != "serial": - self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") + self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYMII( diff --git a/bench/genesys2.py b/bench/genesys2.py index ee1a762..b67ac4b 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -86,7 +86,7 @@ class BenchSoC(SoCCore): # UARTBone --------------------------------------------------------------------------------- if uart != "serial": - self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") + self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYRGMII( diff --git a/bench/kc705.py b/bench/kc705.py index bbc422f..5da2d68 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -88,7 +88,7 @@ class BenchSoC(SoCCore): # UARTBone --------------------------------------------------------------------------------- if uart != "serial": - self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") + self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHY( diff --git a/bench/kcu105.py b/bench/kcu105.py index f4b428a..32e079c 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -105,7 +105,7 @@ class BenchSoC(SoCCore): # UARTBone --------------------------------------------------------------------------------- if uart != "serial": - self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") + self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, diff --git a/bench/xcu1525.py b/bench/xcu1525.py index e5ad96a..34ff862 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -103,7 +103,7 @@ class BenchSoC(SoCCore): # UARTBone --------------------------------------------------------------------------------- if uart != "serial": - self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") + self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart") # Analyzer --------------------------------------------------------------------------------- if with_analyzer: diff --git a/litedram/phy/rpc/arty.py b/litedram/phy/rpc/arty.py index e8184c2..be73587 100755 --- a/litedram/phy/rpc/arty.py +++ b/litedram/phy/rpc/arty.py @@ -260,7 +260,7 @@ class BaseSoC(SoCCore): if dynamic_freq: # UartBone ----------------------------------------------------------------------------- - self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart") + self.add_uartbone(clk_freq=100e6, baudrate=1e6, cd="uart") else: # Etherbone ---------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYMII(