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bench/uartbone: Update with LiteX change.

This commit is contained in:
Florent Kermarrec 2023-07-20 15:44:18 +02:00
parent b291032987
commit 39c0b0356c
6 changed files with 6 additions and 6 deletions
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2
bench/arty.py
View File

@ -95,7 +95,7 @@ class BenchSoC(SoCCore):
# UARTBone --------------------------------------------------------------------------------- # UARTBone ---------------------------------------------------------------------------------
if uart != "serial": if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart")
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYMII( self.submodules.ethphy = LiteEthPHYMII(

2
bench/genesys2.py
View File

@ -86,7 +86,7 @@ class BenchSoC(SoCCore):
# UARTBone --------------------------------------------------------------------------------- # UARTBone ---------------------------------------------------------------------------------
if uart != "serial": if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart")
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII( self.submodules.ethphy = LiteEthPHYRGMII(

2
bench/kc705.py
View File

@ -88,7 +88,7 @@ class BenchSoC(SoCCore):
# UARTBone --------------------------------------------------------------------------------- # UARTBone ---------------------------------------------------------------------------------
if uart != "serial": if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart")
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHY( self.submodules.ethphy = LiteEthPHY(

2
bench/kcu105.py
View File

@ -105,7 +105,7 @@ class BenchSoC(SoCCore):
# UARTBone --------------------------------------------------------------------------------- # UARTBone ---------------------------------------------------------------------------------
if uart != "serial": if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart")
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,

2
bench/xcu1525.py
View File

@ -103,7 +103,7 @@ class BenchSoC(SoCCore):
# UARTBone --------------------------------------------------------------------------------- # UARTBone ---------------------------------------------------------------------------------
if uart != "serial": if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart")
# Analyzer --------------------------------------------------------------------------------- # Analyzer ---------------------------------------------------------------------------------
if with_analyzer: if with_analyzer:

2
litedram/phy/rpc/arty.py
View File

@ -260,7 +260,7 @@ class BaseSoC(SoCCore):
if dynamic_freq: if dynamic_freq:
# UartBone ----------------------------------------------------------------------------- # UartBone -----------------------------------------------------------------------------
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart") self.add_uartbone(clk_freq=100e6, baudrate=1e6, cd="uart")
else: else:
# Etherbone ---------------------------------------------------------------------------- # Etherbone ----------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYMII( self.submodules.ethphy = LiteEthPHYMII(