From 3a5d45bd5ee989cd2816bd5a771438aeeb985bb3 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 5 Nov 2018 12:26:20 +0000
Subject: [PATCH] modules: Add AS4C32M16 32Mx16 SDRAM

Signed-off-by: David Shah <dave@ds0.me>
---
 litedram/modules.py | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 1bfc532..7afaae5 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -136,6 +136,17 @@ class AS4C16M16(SDRAMModule):
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)}
 
 
+class AS4C32M16(SDRAMModule):
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)}
+
+
 # DDR
 class MT46V32M16(SDRAMModule):
     memtype = "DDR"