From 3b4cb273accf6a7936bd574f47f74d4e7d85865b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 19 Dec 2023 09:10:53 +0100 Subject: [PATCH] setup.py: Improve indentation. --- setup.py | 50 +++++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/setup.py b/setup.py index 97101d0..753e9f5 100755 --- a/setup.py +++ b/setup.py @@ -9,20 +9,20 @@ with open("README.md", "r") as fp: setup( - name="litedram", - version="2023.08", - description="Small footprint and configurable DRAM core", - long_description=long_description, - long_description_content_type="text/markdown", - author="Florent Kermarrec", - author_email="florent@enjoy-digital.fr", - url="http://enjoy-digital.fr", - download_url="https://github.com/enjoy-digital/litedram", - test_suite="test", - license="BSD", - python_requires="~=3.6", - install_requires=["pyyaml", "litex"], - extras_require={ + name = "litedram", + version = "2023.08", + description = "Small footprint and configurable DRAM core", + long_description = long_description, + long_description_content_type = "text/markdown", + author = "Florent Kermarrec", + author_email = "florent@enjoy-digital.fr", + url = "http://enjoy-digital.fr", + download_url = "https://github.com/enjoy-digital/litedram", + test_suite = "test", + license = "BSD", + python_requires = "~=3.6", + install_requires = ["pyyaml", "litex"], + extras_require = { "develop": [ "meson" "pexpect" @@ -30,19 +30,19 @@ setup( "requests" ] }, - packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")), - include_package_data=True, - keywords="HDL ASIC FPGA hardware design", - classifiers=[ - "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", - "Environment :: Console", - "Development Status :: 3 - Alpha", - "Intended Audience :: Developers", - "License :: OSI Approved :: BSD License", - "Operating System :: OS Independent", + packages = find_packages(exclude=("test*", "sim*", "doc*", "examples*")), + include_package_data = True, + keywords = "HDL ASIC FPGA hardware design", + classifiers = [ + "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", + "Environment :: Console", + "Development Status :: 3 - Alpha", + "Intended Audience :: Developers", + "License :: OSI Approved :: BSD License", + "Operating System :: OS Independent", "Programming Language :: Python", ], - entry_points={ + entry_points = { "console_scripts": [ "litedram_gen=litedram.gen:main", ],