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litedram
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setup.py: Improve indentation.

This commit is contained in:
Florent Kermarrec 2023-12-19 09:10:53 +01:00
parent e835544d95
commit 3b4cb273ac
1 changed files with 25 additions and 25 deletions
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38
setup.py
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@ -9,20 +9,20 @@ with open("README.md", "r") as fp:
setup(
name="litedram",
version="2023.08",
description="Small footprint and configurable DRAM core",
long_description=long_description,
long_description_content_type="text/markdown",
author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr",
download_url="https://github.com/enjoy-digital/litedram",
test_suite="test",
license="BSD",
python_requires="~=3.6",
install_requires=["pyyaml", "litex"],
extras_require={
name = "litedram",
version = "2023.08",
description = "Small footprint and configurable DRAM core",
long_description = long_description,
long_description_content_type = "text/markdown",
author = "Florent Kermarrec",
author_email = "florent@enjoy-digital.fr",
url = "http://enjoy-digital.fr",
download_url = "https://github.com/enjoy-digital/litedram",
test_suite = "test",
license = "BSD",
python_requires = "~=3.6",
install_requires = ["pyyaml", "litex"],
extras_require = {
"develop": [
"meson"
"pexpect"
@ -30,10 +30,10 @@ setup(
"requests"
]
},
packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
include_package_data=True,
keywords="HDL ASIC FPGA hardware design",
classifiers=[
packages = find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
include_package_data = True,
keywords = "HDL ASIC FPGA hardware design",
classifiers = [
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console",
"Development Status :: 3 - Alpha",
@ -42,7 +42,7 @@ setup(
"Operating System :: OS Independent",
"Programming Language :: Python",
],
entry_points={
entry_points = {
"console_scripts": [
"litedram_gen=litedram.gen:main",
],