From 3d016b2ad5da319e2d37d56843d9c897e8970ac6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 1 Jun 2023 09:58:33 +0200 Subject: [PATCH] frontend/avalon: Use same order on record connections (valid/ready/payload). --- litedram/frontend/avalon.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litedram/frontend/avalon.py b/litedram/frontend/avalon.py index de65716..b1fe9d1 100644 --- a/litedram/frontend/avalon.py +++ b/litedram/frontend/avalon.py @@ -100,20 +100,20 @@ class LiteDRAMAvalonMM2Native(LiteXModule): # Write Data-path. # ---------------- self.comb += [ + wdata_fifo.sink.valid.eq(avalon.write & ~avalon.waitrequest), wdata_fifo.sink.payload.data.eq(avalon.writedata), wdata_fifo.sink.payload.byteenable.eq(avalon.byteenable), - wdata_fifo.sink.valid.eq(avalon.write & ~avalon.waitrequest), - port.wdata.data.eq(wdata_fifo.source.payload.data), - port.wdata.we.eq(wdata_fifo.source.payload.byteenable), port.wdata.valid.eq(wdata_fifo.source.valid), wdata_fifo.source.ready.eq(port.wdata.ready), + port.wdata.data.eq(wdata_fifo.source.payload.data), + port.wdata.we.eq(wdata_fifo.source.payload.byteenable), ] # Read Data-path. # --------------- self.comb += [ + avalon.readdatavalid.eq(port.rdata.valid), port.rdata.ready.eq(1), avalon.readdata.eq(port.rdata.data), - avalon.readdatavalid.eq(port.rdata.valid), ]