diff --git a/litedram/init.py b/litedram/init.py
index dde56a3..2cec01a 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -685,13 +685,16 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
     r += "#define SDRAM_PHY_WRPHASE "+str(wrphase)+"\n"
 
     # Define Read/Write Leveling capability
-    if phytype in ["USDDRPHY", "USPDDRPHY", 'K7DDRPHY', 'V7DDRPHY', 'K7LPDDR4PHY', 'V7LPDDR4PHY']:
+    if phytype in ["USDDRPHY", "USPDDRPHY",
+                   "K7DDRPHY", "V7DDRPHY",
+                   "K7LPDDR4PHY", "V7LPDDR4PHY"]:
         r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n"
-    if phytype in ["USDDRPHY", "USPDDRPHY", 'A7DDRPHY', 'K7DDRPHY', 'V7DDRPHY', 'A7LPDDR4PHY',
-            'K7LPDDR4PHY', 'V7LPDDR4PHY']:
+    if phytype in ["USDDRPHY", "USPDDRPHY",
+                   "A7DDRPHY", "K7DDRPHY", "V7DDRPHY",
+                   "A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
         r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
         r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
-    if phytype in ['K7LPDDR4PHY', 'V7LPDDR4PHY']:
+    if phytype in ["K7LPDDR4PHY", "V7LPDDR4PHY"]:
         r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
     if phytype in ["ECP5DDRPHY"]:
         r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"