From 3f84cc9116488ad4d068636f162447da9517fb58 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 24 Feb 2022 16:33:46 +0100
Subject: [PATCH] ddr3_mr_gen: Also display RZQ/x on configured electrical
 settings.

---
 bench/ddr3_mr_gen.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/bench/ddr3_mr_gen.py b/bench/ddr3_mr_gen.py
index 97785d2..d1b75a4 100755
--- a/bench/ddr3_mr_gen.py
+++ b/bench/ddr3_mr_gen.py
@@ -134,9 +134,9 @@ print(f"cl:  {args.cl}")
 print(f"cwl: {args.cwl}")
 
 print("DDR3 Electrical Settings:")
-print(f"rtt_nom: {args.rtt_nom}")
-print(f"rtt_wr:  {args.rtt_wr}")
-print(f"ron:     {args.ron}")
+print(f"rtt_nom: {args.rtt_nom} {r2rzq(args.rtt_nom)}")
+print(f"rtt_wr:  {args.rtt_wr} {r2rzq(args.rtt_wr)}")
+print(f"ron:     {args.ron} {r2rzq(args.ron)}")
 
 print("Commands to be used with LiteX BIOS:")
 print("sdram_mr_write 0 {:d}".format(format_mr0(