From 3fddff3a1191541544526997da585107d33f1d30 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Oct 2020 17:37:24 +0200 Subject: [PATCH] common/BitSlip: shift output by one bit (allow 1 cycle latency on writes), set reset value to cycles*dw-1. --- litedram/common.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litedram/common.py b/litedram/common.py index 94f9481..f7eb088 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -126,7 +126,7 @@ class BitSlip(Module): # # # - value = Signal(max=cycles*dw) + value = Signal(max=cycles*dw, reset=cycles*dw-1) self.sync += If(self.slp, value.eq(value + 1)) self.sync += If(self.rst, value.eq(0)) @@ -134,7 +134,7 @@ class BitSlip(Module): self.sync += r.eq(Cat(r[dw:], self.i)) cases = {} for i in range(cycles*dw): - cases[i] = self.o.eq(r[i:dw+i]) + cases[i] = self.o.eq(r[i+1:dw+i+1]) self.comb += Case(value, cases) # TappedDelayLine ----------------------------------------------------------------------------------