diff --git a/test/common.py b/test/common.py
index 6b06988..5f7c575 100644
--- a/test/common.py
+++ b/test/common.py
@@ -14,8 +14,8 @@ class DRAMMemory:
     def read_generator(self, dram_port):
         address = 0
         pending = 0
+        yield dram_port.cmd.ready.eq(0)
         while True:
-            yield dram_port.cmd.ready.eq(0)
             yield dram_port.rdata.valid.eq(0)
             if pending:
                 yield dram_port.rdata.valid.eq(1)
@@ -27,16 +27,18 @@ class DRAMMemory:
             elif (yield dram_port.cmd.valid):
                 pending = not (yield dram_port.cmd.we)
                 address = (yield dram_port.cmd.adr)
-                yield
-                yield dram_port.cmd.ready.eq(1)
+                if pending:
+                    yield dram_port.cmd.ready.eq(1)
+                    yield
+                    yield dram_port.cmd.ready.eq(0)
             yield
 
     @passive
     def write_generator(self, dram_port):
         address = 0
         pending = 0
+        yield dram_port.cmd.ready.eq(0)
         while True:
-            yield dram_port.cmd.ready.eq(0)
             yield dram_port.wdata.ready.eq(0)
             if pending:
                 yield dram_port.wdata.ready.eq(1)
@@ -49,7 +51,8 @@ class DRAMMemory:
             elif (yield dram_port.cmd.valid):
                 pending = (yield dram_port.cmd.we)
                 address = (yield dram_port.cmd.adr)
-                yield dram_port.cmd.ready.eq(1)
-                yield
-                yield dram_port.cmd.ready.eq(0)
+                if pending:
+                    yield dram_port.cmd.ready.eq(1)
+                    yield
+                    yield dram_port.cmd.ready.eq(0)
             yield
diff --git a/test/downconverter_tb.py b/test/downconverter_tb.py
index 6ca1f66..ece87c9 100644
--- a/test/downconverter_tb.py
+++ b/test/downconverter_tb.py
@@ -30,12 +30,24 @@ def main_generator(dut):
         while (yield dut.user_port.wdata.ready) == 0:
             yield
         yield
+    # read
+    yield dut.user_port.rdata.ready.eq(1)
+    for i in range(8):
+        yield dut.user_port.cmd.valid.eq(1)
+        yield dut.user_port.cmd.we.eq(0)
+        yield dut.user_port.cmd.adr.eq(i)
+        yield
+        while (yield dut.user_port.cmd.ready) == 0:
+            yield
+        yield dut.user_port.cmd.valid.eq(0)
+        yield
 
 if __name__ == "__main__":
     tb = TB()
     generators = {
         "sys" :   [main_generator(tb),
-                   tb.memory.write_generator(tb.internal_port)]
+                   tb.memory.write_generator(tb.internal_port),
+                   tb.memory.read_generator(tb.internal_port)]
     }
     clocks = {"sys": 10}
     run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
diff --git a/test/upconverter_tb.py b/test/upconverter_tb.py
index 2543ebf..7c66884 100644
--- a/test/upconverter_tb.py
+++ b/test/upconverter_tb.py
@@ -37,12 +37,25 @@ def main_generator(dut):
             yield
         yield dut.user_port.wdata.valid.eq(0)
         yield
+    # read
+    for i in range(8):
+        yield dut.user_port.rdata.ready.eq(1)
+        for j in range(2):
+            yield dut.user_port.cmd.valid.eq(1)
+            yield dut.user_port.cmd.we.eq(0)
+            yield dut.user_port.cmd.adr.eq(i)
+            yield
+            while (yield dut.user_port.cmd.ready) == 0:
+                yield
+            yield dut.user_port.cmd.valid.eq(0)
+            yield
 
 if __name__ == "__main__":
     tb = TB()
     generators = {
         "sys" :   [main_generator(tb),
-                   tb.memory.write_generator(tb.internal_port)]
+                   tb.memory.write_generator(tb.internal_port),
+                   tb.memory.read_generator(tb.internal_port)]
     }
     clocks = {"sys": 10}
     run_simulation(tb, generators, clocks, vcd_name="sim.vcd")