diff --git a/litedram/modules.py b/litedram/modules.py
index cbae78f..62cef5d 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -253,7 +253,7 @@ class MT41J128M16(SDRAMModule):
     tRCD_800 = 13.1
     tWR_800  = 13.1
     tRFC_800 = 64
-    tFAW_800 = (20, None)
+    tFAW_800 = (None, 50)
     tRC_800 = 50.625
     tRAS_800 = 37.5
     # DDR3-1066
@@ -261,7 +261,7 @@ class MT41J128M16(SDRAMModule):
     tRCD_1066 = 13.1
     tWR_1066  = 13.1
     tRFC_1066 = 86
-    tFAW_1066 = (27, None)
+    tFAW_1066 = (None, 50)
     tRC_1066 = 50.625
     tRAS_1066 = 37.5
     # DDR3-1333
@@ -269,7 +269,7 @@ class MT41J128M16(SDRAMModule):
     tRCD_1333 = 13.5
     tWR_1333  = 13.5
     tRFC_1333 = 107
-    tFAW_1333 = (30, None)
+    tFAW_1333 = (None, 45)
     tRC_1333 = 49.5
     tRAS_1333 = 36
     # DDR3-1600
@@ -277,7 +277,7 @@ class MT41J128M16(SDRAMModule):
     tRCD_1600 = 13.75
     tWR_1600  = 13.75
     tRFC_1600 = 128
-    tFAW_1600 = (32, None)
+    tFAW_1600 = (None, 40)
     tRC_1600 = 48.75
     tRAS_1600 = 35
     # API retro-compatibility
@@ -352,13 +352,13 @@ class MT8JTF12864(SDRAMModule):
     tRCD_1066 = 15
     tWR_1066  = 15
     tRFC_1066 = 86
-    tFAW_1066 = (27, None)
+    tFAW_1066 = (None, 50)
     # DDR3-1333
     tRP_1333  = 15
     tRCD_1333 = 15
     tWR_1333  = 15
     tRFC_1333 = 107
-    tFAW_1333 = (30, None)
+    tFAW_1333 = (None, 45)
     # API retro-compatibility
     tRP  = tRP_1333
     tRCD = tRCD_1333
@@ -382,19 +382,19 @@ class MT18KSF1G72HZ(SDRAMModule):
     tRCD_1066 = 15
     tWR_1066  = 15
     tRFC_1066 = 86
-    tFAW_1066 = (27, None)
+    tFAW_1066 = (None, 50)
     # DDR3-1333
     tRP_1333  = 15
     tRCD_1333 = 15
     tWR_1333  = 15
     tRFC_1333 = 107
-    tFAW_1333 = (30, None)
+    tFAW_1333 = (None, 45)
     # DDR3-1600
     tRP_1600  = 13.125
     tRCD_1600 = 13.125
     tWR_1600  = 13.125
     tRFC_1600 = 128
-    tFAW_1600 = (32, None)
+    tFAW_1600 = (None, 40)
     # API retro-compatibility
     tRP  = tRP_1600
     tRCD = tRCD_1600