From 426ae23d2aff8273126705c6e66a6b0a70c1c5eb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Oct 2018 11:48:15 +0200 Subject: [PATCH] examples/litedram_gen: add sdram_module_speedgrade parameter --- examples/arty_config.py | 1 + examples/genesys2_config.py | 1 + examples/litedram_gen.py | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/examples/arty_config.py b/examples/arty_config.py index 373421b..20bca1c 100644 --- a/examples/arty_config.py +++ b/examples/arty_config.py @@ -8,6 +8,7 @@ core_config = { # modules / phy "sdram_module": MT41K128M16, "sdram_module_nb": 1, + "sdram_module_speedgrade": "1066", "sdram_rank_nb": 1, "sdram_phy": A7DDRPHY, diff --git a/examples/genesys2_config.py b/examples/genesys2_config.py index 1480342..2ad175d 100644 --- a/examples/genesys2_config.py +++ b/examples/genesys2_config.py @@ -8,6 +8,7 @@ core_config = { # modules / phy "sdram_module": MT41J256M16, "sdram_module_nb": 2, + "sdram_module_speedgrade": "1333", "sdram_rank_nb": 1, "sdram_phy": K7DDRPHY, diff --git a/examples/litedram_gen.py b/examples/litedram_gen.py index 2e1fbd6..a6f82ae 100755 --- a/examples/litedram_gen.py +++ b/examples/litedram_gen.py @@ -210,7 +210,7 @@ class LiteDRAMCore(SoCSDRAM): rtt_nom=core_config["rtt_nom"], rtt_wr=core_config["rtt_wr"], ron=core_config["ron"]) - sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4") + sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4", speedgrade=core_config["sdram_module_speedgrade"]) controller_settings = controller_settings=ControllerSettings( cmd_buffer_depth=core_config["cmd_buffer_depth"], read_time=core_config["read_time"],