diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h index 5ee2cdb..6850c6e 100644 --- a/test/reference/ddr3_init.h +++ b/test/reference/ddr3_init.h @@ -1,19 +1,20 @@ #ifndef __GENERATED_SDRAM_PHY_H #define __GENERATED_SDRAM_PHY_H + #include #include -#define DFII_CONTROL_SEL 0x01 -#define DFII_CONTROL_CKE 0x02 -#define DFII_CONTROL_ODT 0x04 -#define DFII_CONTROL_RESET_N 0x08 +#define DFII_CONTROL_SEL 0x01 +#define DFII_CONTROL_CKE 0x02 +#define DFII_CONTROL_ODT 0x04 +#define DFII_CONTROL_RESET_N 0x08 -#define DFII_COMMAND_CS 0x01 -#define DFII_COMMAND_WE 0x02 -#define DFII_COMMAND_CAS 0x04 -#define DFII_COMMAND_RAS 0x08 -#define DFII_COMMAND_WRDATA 0x10 -#define DFII_COMMAND_RDDATA 0x20 +#define DFII_COMMAND_CS 0x01 +#define DFII_COMMAND_WE 0x02 +#define DFII_COMMAND_CAS 0x04 +#define DFII_COMMAND_RAS 0x08 +#define DFII_COMMAND_WRDATA 0x10 +#define DFII_COMMAND_RDDATA 0x20 #define SDRAM_PHY_K7DDRPHY #define SDRAM_PHY_XDR 2 @@ -26,8 +27,8 @@ #define SDRAM_PHY_RDPHASE 1 #define SDRAM_PHY_WRPHASE 2 #define SDRAM_PHY_WRITE_LEVELING_CAPABLE -#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE +#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE #define SDRAM_PHY_READ_LEVELING_CAPABLE #define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8) #define SDRAM_PHY_DELAYS 32 @@ -37,47 +38,48 @@ void cdelay(int i); __attribute__((unused)) static inline void command_p0(int cmd) { - sdram_dfii_pi0_command_write(cmd); - sdram_dfii_pi0_command_issue_write(1); + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); } __attribute__((unused)) static inline void command_p1(int cmd) { - sdram_dfii_pi1_command_write(cmd); - sdram_dfii_pi1_command_issue_write(1); + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); } __attribute__((unused)) static inline void command_p2(int cmd) { - sdram_dfii_pi2_command_write(cmd); - sdram_dfii_pi2_command_issue_write(1); + sdram_dfii_pi2_command_write(cmd); + sdram_dfii_pi2_command_issue_write(1); } __attribute__((unused)) static inline void command_p3(int cmd) { - sdram_dfii_pi3_command_write(cmd); - sdram_dfii_pi3_command_issue_write(1); + sdram_dfii_pi3_command_write(cmd); + sdram_dfii_pi3_command_issue_write(1); } #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE -static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){ - switch (phase) { - case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR; +static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase) +{ + switch (phase) { + case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR; case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR; case 2: return CSR_SDRAM_DFII_PI2_WRDATA_ADDR; case 3: return CSR_SDRAM_DFII_PI3_WRDATA_ADDR; - default: return 0; - } + default: return 0; + } } - -static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){ - switch (phase) { - case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR; +static inline unsigned long sdram_dfii_pix_rddata_addr(int phase) +{ + switch (phase) { + case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR; case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR; case 2: return CSR_SDRAM_DFII_PI2_RDDATA_ADDR; case 3: return CSR_SDRAM_DFII_PI3_RDDATA_ADDR; - default: return 0; - } + default: return 0; + } } - + #define DDRX_MR_WRLVL_ADDRESS 1 #define DDRX_MR_WRLVL_RESET 6 #define DDRX_MR_WRLVL_BIT 7 @@ -124,4 +126,5 @@ static inline void init_sequence(void) cdelay(200); } -#endif + +#endif /* __GENERATED_SDRAM_PHY_H */ diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h index 2f6a261..5074a10 100644 --- a/test/reference/ddr4_init.h +++ b/test/reference/ddr4_init.h @@ -1,19 +1,20 @@ #ifndef __GENERATED_SDRAM_PHY_H #define __GENERATED_SDRAM_PHY_H + #include #include -#define DFII_CONTROL_SEL 0x01 -#define DFII_CONTROL_CKE 0x02 -#define DFII_CONTROL_ODT 0x04 -#define DFII_CONTROL_RESET_N 0x08 +#define DFII_CONTROL_SEL 0x01 +#define DFII_CONTROL_CKE 0x02 +#define DFII_CONTROL_ODT 0x04 +#define DFII_CONTROL_RESET_N 0x08 -#define DFII_COMMAND_CS 0x01 -#define DFII_COMMAND_WE 0x02 -#define DFII_COMMAND_CAS 0x04 -#define DFII_COMMAND_RAS 0x08 -#define DFII_COMMAND_WRDATA 0x10 -#define DFII_COMMAND_RDDATA 0x20 +#define DFII_COMMAND_CS 0x01 +#define DFII_COMMAND_WE 0x02 +#define DFII_COMMAND_CAS 0x04 +#define DFII_COMMAND_RAS 0x08 +#define DFII_COMMAND_WRDATA 0x10 +#define DFII_COMMAND_RDDATA 0x20 #define SDRAM_PHY_USDDRPHY #define SDRAM_PHY_XDR 2 @@ -36,45 +37,46 @@ void cdelay(int i); __attribute__((unused)) static inline void command_p0(int cmd) { - sdram_dfii_pi0_command_write(cmd); - sdram_dfii_pi0_command_issue_write(1); + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); } __attribute__((unused)) static inline void command_p1(int cmd) { - sdram_dfii_pi1_command_write(cmd); - sdram_dfii_pi1_command_issue_write(1); + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); } __attribute__((unused)) static inline void command_p2(int cmd) { - sdram_dfii_pi2_command_write(cmd); - sdram_dfii_pi2_command_issue_write(1); + sdram_dfii_pi2_command_write(cmd); + sdram_dfii_pi2_command_issue_write(1); } __attribute__((unused)) static inline void command_p3(int cmd) { - sdram_dfii_pi3_command_write(cmd); - sdram_dfii_pi3_command_issue_write(1); + sdram_dfii_pi3_command_write(cmd); + sdram_dfii_pi3_command_issue_write(1); } #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE -static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){ - switch (phase) { - case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR; +static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase) +{ + switch (phase) { + case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR; case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR; case 2: return CSR_SDRAM_DFII_PI2_WRDATA_ADDR; case 3: return CSR_SDRAM_DFII_PI3_WRDATA_ADDR; - default: return 0; - } + default: return 0; + } } - -static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){ - switch (phase) { - case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR; +static inline unsigned long sdram_dfii_pix_rddata_addr(int phase) +{ + switch (phase) { + case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR; case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR; case 2: return CSR_SDRAM_DFII_PI2_RDDATA_ADDR; case 3: return CSR_SDRAM_DFII_PI3_RDDATA_ADDR; - default: return 0; - } + default: return 0; + } } #define DDRX_MR_WRLVL_ADDRESS 1 @@ -138,4 +140,5 @@ static inline void init_sequence(void) cdelay(200); } -#endif + +#endif /* __GENERATED_SDRAM_PHY_H */ diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h index 235f0ae..9054b25 100644 --- a/test/reference/sdr_init.h +++ b/test/reference/sdr_init.h @@ -1,19 +1,20 @@ #ifndef __GENERATED_SDRAM_PHY_H #define __GENERATED_SDRAM_PHY_H + #include #include -#define DFII_CONTROL_SEL 0x01 -#define DFII_CONTROL_CKE 0x02 -#define DFII_CONTROL_ODT 0x04 -#define DFII_CONTROL_RESET_N 0x08 +#define DFII_CONTROL_SEL 0x01 +#define DFII_CONTROL_CKE 0x02 +#define DFII_CONTROL_ODT 0x04 +#define DFII_CONTROL_RESET_N 0x08 -#define DFII_COMMAND_CS 0x01 -#define DFII_COMMAND_WE 0x02 -#define DFII_COMMAND_CAS 0x04 -#define DFII_COMMAND_RAS 0x08 -#define DFII_COMMAND_WRDATA 0x10 -#define DFII_COMMAND_RDDATA 0x20 +#define DFII_COMMAND_CS 0x01 +#define DFII_COMMAND_WE 0x02 +#define DFII_COMMAND_CAS 0x04 +#define DFII_COMMAND_RAS 0x08 +#define DFII_COMMAND_WRDATA 0x10 +#define DFII_COMMAND_RDDATA 0x20 #define SDRAM_PHY_GENSDRPHY #define SDRAM_PHY_XDR 1 @@ -30,26 +31,27 @@ void cdelay(int i); __attribute__((unused)) static inline void command_p0(int cmd) { - sdram_dfii_pi0_command_write(cmd); - sdram_dfii_pi0_command_issue_write(1); + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); } #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE -static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){ - switch (phase) { - case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR; - default: return 0; - } +static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase) +{ + switch (phase) { + case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR; + default: return 0; + } } - -static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){ - switch (phase) { - case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR; - default: return 0; - } +static inline unsigned long sdram_dfii_pix_rddata_addr(int phase) +{ + switch (phase) { + case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR; + default: return 0; + } } - + static inline void init_sequence(void) { /* Bring CKE high */ @@ -93,4 +95,5 @@ static inline void init_sequence(void) cdelay(200); } -#endif + +#endif /* __GENERATED_SDRAM_PHY_H */