From 4326fe7f36699ae219dbaccc38d9176b749f6d8e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 13 Jul 2021 14:57:42 +0200 Subject: [PATCH] bench/kcu105/xcu1525: Also use PHYPadsReducer to easily test various DFI sizes. --- bench/kcu105.py | 6 ++++-- bench/xcu1525.py | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/bench/kcu105.py b/bench/kcu105.py index 180c0a5..659f91a 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -19,8 +19,9 @@ from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * -from litedram.modules import EDY4016A +from litedram.common import PHYPadsReducer from litedram.phy import usddrphy +from litedram.modules import EDY4016A from liteeth.phy.ku_1000basex import KU_1000BASEX @@ -91,7 +92,8 @@ class BenchSoC(SoCCore): self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- - self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), + self.submodules.ddrphy = usddrphy.USDDRPHY( + pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]), memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) diff --git a/bench/xcu1525.py b/bench/xcu1525.py index 57d3847..710801e 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -19,6 +19,7 @@ from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * +from litedram.common import PHYPadsReducer from litedram.modules import MT40A512M8 from litedram.phy import usddrphy @@ -87,7 +88,8 @@ class BenchSoC(SoCCore): self.submodules.crg = _CRG(platform, sys_clk_freq, channel) # DDR4 SDRAM ------------------------------------------------------------------------------- - self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", channel), + self.submodules.ddrphy = usddrphy.USPDDRPHY( + pads = PHYPadsReducer(platform.request("ddram", channel), [0, 1, 2, 3, 4, 5, 6, 7]), memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6)