From 4815be2feffb355af3e714a069741742c01c139d Mon Sep 17 00:00:00 2001
From: Christian Klarhorst <cklarhor@techfak.uni-bielefeld.de>
Date: Sun, 30 Oct 2022 10:18:49 +0100
Subject: [PATCH] Add new module MT46H128M16

---
 litedram/modules.py | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 6d215ee..af517b1 100755
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -590,6 +590,14 @@ class MT46H64M16(LPDDRModule):
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
 
+class MT46H128M16(LPDDRModule):
+    # geometry
+    nbanks = 4
+    nrows  = 16384
+    ncols  = 2048
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
 
 class MT46H32M32(LPDDRModule):
     # geometry