diff --git a/litedram/modules.py b/litedram/modules.py
index 72f544c..550557e 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -170,7 +170,7 @@ class MT46H32M32(SDRAMModule):
     nrows  = 8192
     ncols  = 1024
     # timings
-    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(1, None), tCCD=(1, None), tRRD=None)
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=72, tFAW=None, tRC=None, tRAS=None)}