From 48c17ce8a4afb7fa94d68dc7ed498bb94845709c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 2 Oct 2018 18:53:13 +0200 Subject: [PATCH] modules: fix tWTR regression on MT46H32M32 --- litedram/modules.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/modules.py b/litedram/modules.py index 72f544c..550557e 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -170,7 +170,7 @@ class MT46H32M32(SDRAMModule): nrows = 8192 ncols = 1024 # timings - technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(1, None), tCCD=(1, None), tRRD=None) + technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None) speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=72, tFAW=None, tRC=None, tRAS=None)}