diff --git a/litedram/core/controller.py b/litedram/core/controller.py
index 2b2fa3b..3932e23 100644
--- a/litedram/core/controller.py
+++ b/litedram/core/controller.py
@@ -40,7 +40,13 @@ class ControllerSettings(Settings):
         with_auto_precharge = True,
 
         # Address mapping
-        address_mapping     = "ROW_BANK_COL"):
+        address_mapping     = "ROW_BANK_COL",
+
+        # bank_byte_alignment specify how many bytes should be in between each bank change (minimum).
+        # This is usefull when you want to match a L2 cache sets size.
+        # For instance you have a L2 cache of 256KB with 4 ways => Sets size of 256KB/4=64KB
+        # => Ideal bank_byte_alignment = 0x10000
+        bank_byte_alignment     = 0):
         self.set_attributes(locals())
 
 # Controller ---------------------------------------------------------------------------------------
diff --git a/litedram/core/crossbar.py b/litedram/core/crossbar.py
index cdf943a..64da8e6 100644
--- a/litedram/core/crossbar.py
+++ b/litedram/core/crossbar.py
@@ -127,7 +127,7 @@ class LiteDRAMCrossbar(Module):
         nmasters   = len(self.masters)
 
         # Address mapping --------------------------------------------------------------------------
-        cba_shifts = {"ROW_BANK_COL": controller.settings.geom.colbits - controller.address_align}
+        cba_shifts = {"ROW_BANK_COL": max(controller.settings.geom.colbits - controller.address_align, log2_int(controller.settings.bank_byte_alignment //(controller.data_width // 8))) }
         cba_shift = cba_shifts[controller.settings.address_mapping]
         m_ba      = [m.get_bank_address(self.bank_bits, cba_shift)for m in self.masters]
         m_rca     = [m.get_row_column_address(self.bank_bits, self.rca_bits, cba_shift) for m in self.masters]