diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py
index 74fffa5..4fb5727 100644
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@@ -29,7 +29,7 @@ class S7DDRPHY(Module, AutoCSR):
         nphases          = 4,
         sys_clk_freq     = 100e6,
         iodelay_clk_freq = 200e6,
-        cmd_latency      = 1,
+        cmd_latency      = 0,
         cmd_delay        = None):
         assert not (memtype == "DDR3" and nphases == 2)
         phytype     = self.__class__.__name__
@@ -461,5 +461,5 @@ class K7DDRPHY(S7DDRPHY):
 # Xilinx Artix7 (S7DDRPHY without odelay, sys2/4x_dqs generated in CRG with 90° phase vs sys2/4x) --
 
 class A7DDRPHY(S7DDRPHY):
-    def __init__(self, pads, cmd_latency=0, **kwargs):
-        S7DDRPHY.__init__(self, pads, with_odelay=False, cmd_latency=cmd_latency, **kwargs)
+    def __init__(self, pads, **kwargs):
+        S7DDRPHY.__init__(self, pads, with_odelay=False, **kwargs)
diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py
index 73f2d21..2c4ca82 100644
--- a/litedram/phy/usddrphy.py
+++ b/litedram/phy/usddrphy.py
@@ -28,7 +28,7 @@ class USDDRPHY(Module, AutoCSR):
         memtype          = "DDR3",
         sys_clk_freq     = 100e6,
         iodelay_clk_freq = 200e6,
-        cmd_latency      = 1,
+        cmd_latency      = 0,
         cmd_delay        = None,
         is_rdimm         = False):
         phytype     = self.__class__.__name__