From 49f48130e7ca207679ada342dfaadf11e13a430d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 31 May 2023 18:02:12 +0200 Subject: [PATCH] frontend/avalon: Always go through wdata_fifo. --- litedram/frontend/avalon.py | 39 ++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/litedram/frontend/avalon.py b/litedram/frontend/avalon.py index fc3f886..68e3f3d 100644 --- a/litedram/frontend/avalon.py +++ b/litedram/frontend/avalon.py @@ -20,7 +20,7 @@ from litedram.frontend.adapter import LiteDRAMNativePortConverter # LiteDRAMAvalonMM2Native -------------------------------------------------------------------------- class LiteDRAMAvalonMM2Native(LiteXModule): - def __init__(self, avalon, port, *, max_burst_length=16, base_address=0x00000000, burst_increment=1): + def __init__(self, avalon, port, max_burst_length=16, base_address=0x00000000, burst_increment=1): # Parameters. avalon_data_width = len(avalon.writedata) port_data_width = 2**int(log2(len(port.wdata.data))) # Round to lowest power 2 @@ -48,8 +48,6 @@ class LiteDRAMAvalonMM2Native(LiteXModule): burst_count = Signal(9) address = Signal(port.address_width) address_offset = Signal(port.address_width) - byteenable = Signal(avalon_data_width//8) - writedata = Signal(avalon_data_width) latch = Signal() cmd_ready_seen = Signal() cmd_ready_count = Signal(9) @@ -65,8 +63,6 @@ class LiteDRAMAvalonMM2Native(LiteXModule): self.sync += [ If(latch, - byteenable.eq(avalon.byteenable), - writedata.eq(avalon.writedata), burst_count.eq(avalon.burstcount), address.eq(avalon.address - address_offset), ) @@ -110,13 +106,7 @@ class LiteDRAMAvalonMM2Native(LiteXModule): fsm.act("SINGLE_WRITE", avalon.waitrequest.eq(1), - port.rdata.ready.eq(0), - - port.wdata.data.eq(writedata), - port.wdata.valid.eq(1), - port.wdata.we.eq(byteenable), - - If(port.wdata.ready, + If(port.wdata.valid & port.wdata.ready, NextState("START") ) ) @@ -124,7 +114,6 @@ class LiteDRAMAvalonMM2Native(LiteXModule): fsm.act("SINGLE_READ", avalon.waitrequest.eq(1), port.rdata.ready.eq(1), - If(port.rdata.valid, avalon.readdata.eq(port.rdata.data), avalon.readdatavalid.eq(1), @@ -133,8 +122,21 @@ class LiteDRAMAvalonMM2Native(LiteXModule): ) ) - self.cmd_fifo = cmd_fifo = stream.SyncFIFO(cmd_layout, max_burst_length) + + # Write Data-Path. self.wdata_fifo = wdata_fifo = stream.SyncFIFO(wdata_layout, max_burst_length) + self.comb += [ + wdata_fifo.sink.payload.data.eq(avalon.writedata), + wdata_fifo.sink.payload.byteenable.eq(avalon.byteenable), + wdata_fifo.sink.valid.eq(avalon.write & ~avalon.waitrequest), + + port.wdata.data.eq(wdata_fifo.source.payload.data), + port.wdata.we.eq(wdata_fifo.source.payload.byteenable), + port.wdata.valid.eq(wdata_fifo.source.valid), + wdata_fifo.source.ready.eq(port.wdata.ready), + ] + + self.cmd_fifo = cmd_fifo = stream.SyncFIFO(cmd_layout, max_burst_length) fsm.act("BURST_WRITE", # FIFO producer @@ -142,10 +144,6 @@ class LiteDRAMAvalonMM2Native(LiteXModule): cmd_fifo.sink.payload.address.eq(address), cmd_fifo.sink.valid.eq(avalon.write & ~avalon.waitrequest), - wdata_fifo.sink.payload.data.eq(avalon.writedata), - wdata_fifo.sink.payload.byteenable.eq(avalon.byteenable), - wdata_fifo.sink.valid.eq(avalon.write & ~avalon.waitrequest), - If(avalon.write & (burst_count > 0), If(cmd_fifo.sink.ready & cmd_fifo.sink.valid, NextValue(burst_count, burst_count - 1), @@ -165,10 +163,7 @@ class LiteDRAMAvalonMM2Native(LiteXModule): port.cmd.valid.eq(cmd_fifo.source.valid & (0 < wdata_fifo.level)), cmd_fifo.source.ready.eq(port.cmd.ready), - port.wdata.data.eq(wdata_fifo.source.payload.data), - port.wdata.we.eq(wdata_fifo.source.payload.byteenable), - port.wdata.valid.eq(wdata_fifo.source.valid), - wdata_fifo.source.ready.eq(port.wdata.ready), + ) fsm.act("BURST_READ",