diff --git a/test/phy_common.py b/test/phy_common.py
index db79529..e5af262 100644
--- a/test/phy_common.py
+++ b/test/phy_common.py
@@ -10,9 +10,12 @@ import itertools
 from collections import defaultdict
 from typing import Mapping, Sequence
 
+from migen import *
+
 from litedram.phy import dfi
 from litedram.phy.utils import chunks
 
+from test.test_phy_utils import run_simulation as _run_simulation
 
 BOLD = '\033[1m'
 HIGHLIGHT = '\033[91m'
@@ -22,6 +25,32 @@ def highlight(s, hl=True):
     return BOLD + (HIGHLIGHT if hl else '') + s + CLEAR
 
 
+def run_simulation(dut, generators, clocks, debug_clocks=False, **kwargs):
+    """Wrapper that can be used to easily debug clock configuration"""
+
+    if not isinstance(generators, dict):
+        assert "sys" in clocks
+    else:
+        for clk in generators:
+            assert clk in clocks, clk
+
+    if debug_clocks:
+        class DUT(Module):
+            def __init__(self, dut):
+                self.submodules.dut = dut
+                for clk in clocks:
+                    setattr(self.clock_domains, "cd_{}".format(clk), ClockDomain(clk))
+                    cd = getattr(self, 'cd_{}'.format(clk))
+                    self.comb += cd.rst.eq(0)
+
+                    s = Signal(4, name='dbg_{}'.format(clk))
+                    sd = getattr(self.sync, clk)
+                    sd += s.eq(s + 1)
+        dut = DUT(dut)
+
+    _run_simulation(dut, generators, clocks, **kwargs)
+
+
 class PadsHistory(defaultdict):
     """Storage for hisotry of per-pad values with human-readable printing
 
@@ -64,6 +93,7 @@ class PadChecker:
     """Helper class for defining expected sequences on pads"""
     def __init__(self, pads, signals: Mapping[str, str]):
         # signals: {sig: values}, values: a string of '0'/'1'/'x'/' '
+        signals = {clk: values.replace(' ', '') for clk, values in signals.items()}
         self.pads = pads
         self.signals = signals
         self.history = PadsHistory()  # registered values
diff --git a/test/test_lpddr4.py b/test/test_lpddr4.py
index 3861535..85d3cf1 100644
--- a/test/test_lpddr4.py
+++ b/test/test_lpddr4.py
@@ -16,8 +16,7 @@ from litedram.phy.utils import bit
 from litedram.phy.lpddr4.simphy import LPDDR4SimPHY, DoubleRateLPDDR4SimPHY
 from litedram.phy.lpddr4 import simsoc
 
-from test.phy_common import DFISequencer, PadChecker
-from test.test_phy_utils import run_simulation as _run_simulation
+from test.phy_common import DFISequencer, PadChecker, run_simulation as _run_simulation
 
 
 # Migen simulator supports reset signals so we could add CRG to start all the signals
diff --git a/test/test_phy_utils.py b/test/test_phy_utils.py
index 4cea8c8..24caaa4 100644
--- a/test/test_phy_utils.py
+++ b/test/test_phy_utils.py
@@ -11,27 +11,7 @@ from migen import *
 
 from litedram.phy.utils import Serializer, Deserializer, Latency, chunks, bit
 
-from litex.gen.sim import run_simulation as _run_simulation
-
-
-def run_simulation(dut, generators, clocks, debug_clocks=False, **kwargs):
-    """Wrapper that can be used to easily debug clock configuration"""
-
-    if debug_clocks:
-        class DUT(Module):
-            def __init__(self, dut):
-                self.submodules.dut = dut
-                for clk in clocks:
-                    setattr(self.clock_domains, "cd_{}".format(clk), ClockDomain(clk))
-                    cd = getattr(self, 'cd_{}'.format(clk))
-                    self.comb += cd.rst.eq(0)
-
-                    s = Signal(4, name='dbg_{}'.format(clk))
-                    sd = getattr(self.sync, clk)
-                    sd += s.eq(s + 1)
-        dut = DUT(dut)
-
-    _run_simulation(dut, generators, clocks, **kwargs)
+from test.phy_common import run_simulation
 
 
 class TestSimSerializers(unittest.TestCase):