From 4adfff2c8b744df38ffcb2498bf2f74311656bb9 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 30 Sep 2021 15:44:14 +0200
Subject: [PATCH] modules: Add IS43TR16512B.

---
 litedram/modules.py | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 2e62948..194f25b 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -773,6 +773,17 @@ class IS43TR16256A(DDR3Module):
     }
     speedgrade_timings["default"] = speedgrade_timings["1600"]
 
+class IS43TR16512B(DDR3Module):
+    # geometry
+    nbanks = 8
+    nrows  = 65536
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
+    speedgrade_timings = {
+        "1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=35),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["1600"]
 
 # DDR3 (SO-DIMM) -----------------------------------------------------------------------------------