From 4c1b97b465d374a5b9db076589971c0a2b30b69d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 3 May 2016 17:45:57 +0200 Subject: [PATCH] core/refresher: remove req/ack signal and use stream --- litedram/core/multiplexer.py | 6 +++--- litedram/core/refresher.py | 16 +++++++++------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/litedram/core/multiplexer.py b/litedram/core/multiplexer.py index 8864421..fd99a6a 100644 --- a/litedram/core/multiplexer.py +++ b/litedram/core/multiplexer.py @@ -159,7 +159,7 @@ class Multiplexer(Module, AutoCSR): write_time_en, max_write_time = anti_starvation(settings.write_time) # Refresh - self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines] + self.comb += [bm.refresh_req.eq(refresher.cmd.valid) for bm in bank_machines] go_to_refresh = Signal() bm_refresh_gnts = [bm.refresh_gnt for bm in bank_machines] self.comb += go_to_refresh.eq(reduce(and_, bm_refresh_gnts)) @@ -228,8 +228,8 @@ class Multiplexer(Module, AutoCSR): ) fsm.act("REFRESH", steerer.sel[0].eq(STEER_REFRESH), - refresher.ack.eq(1), - If(~refresher.req, + refresher.cmd.ready.eq(1), + If(refresher.cmd.valid & refresher.cmd.last, NextState("READ") ) ) diff --git a/litedram/core/refresher.py b/litedram/core/refresher.py index d4e4829..6a5db29 100644 --- a/litedram/core/refresher.py +++ b/litedram/core/refresher.py @@ -1,15 +1,16 @@ from litex.gen import * from litex.gen.genlib.misc import timeline, WaitTimer +from litex.soc.interconnect import stream + from litedram.core.multiplexer import * class Refresher(Module): def __init__(self, settings): - self.req = Signal() - self.ack = Signal() # 1st command 1 cycle after assertion of ack - self.cmd = cmd = Record(cmd_request_layout(settings.geom.addressbits, - settings.geom.bankbits)) + # 1st command 1 cycle after assertion of ready + self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(settings.geom.addressbits, + settings.geom.bankbits)) # # # @@ -51,15 +52,16 @@ class Refresher(Module): ) ) fsm.act("WAIT_GRANT", - self.req.eq(1), - If(self.ack, + cmd.valid.eq(1), + If(cmd.ready, seq_start.eq(1), NextState("WAIT_SEQ") ) ) fsm.act("WAIT_SEQ", - self.req.eq(1), + cmd.valid.eq(1), If(seq_done, + cmd.last.eq(1), NextState("IDLE") ) )