From 4fdb9a2cf2a2dc0767f18c848d03713a42e3d325 Mon Sep 17 00:00:00 2001
From: Benjamin Herrenschmidt <benh@amazon.com>
Date: Wed, 22 Sep 2021 21:01:56 +1000
Subject: [PATCH] Fix generation with no CPU

The various UART bits in there need to be skipped

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 litedram/gen.py | 54 +++++++++++++++++++++++++------------------------
 1 file changed, 28 insertions(+), 26 deletions(-)

diff --git a/litedram/gen.py b/litedram/gen.py
index bb56af9..583125a 100755
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -466,11 +466,6 @@ class LiteDRAMCoreControl(Module, AutoCSR):
 
 class LiteDRAMCore(SoCCore):
     def __init__(self, platform, core_config, **kwargs):
-        platform.add_extension(get_common_ios())
-        if core_config["uart"] == "fifo":
-            platform.add_extension(get_uart_fifo_ios())
-        else:
-            platform.add_extension(get_uart_std_ios())
 
         # Parameters -------------------------------------------------------------------------------
         sys_clk_freq   = core_config["sys_clk_freq"]
@@ -485,39 +480,46 @@ class LiteDRAMCore(SoCCore):
             kwargs["with_timer"]           = False
             kwargs["with_ctrl"]            = False
 
+        platform.add_extension(get_common_ios())
+        if cpu_type is not None:
+            if core_config["uart"] == "fifo":
+                platform.add_extension(get_uart_fifo_ios())
+            else:
+                platform.add_extension(get_uart_std_ios())
+
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
             cpu_type       = cpu_type,
             cpu_variant    = cpu_variant,
             csr_data_width = csr_data_width,
-            with_uart      = False,
             **kwargs)
 
         # UART -------------------------------------------------------------------------------------
-        assert uart_type in ["rs232", "fifo"]
-        if uart_type == "fifo":
-            uart_interface = RS232PHYInterface()
-            self.submodules.uart = UART(uart_interface, tx_fifo_depth=1, rx_fifo_depth=1)
-            uart_tx_pads = platform.request("uart_tx")
-            uart_rx_pads = platform.request("uart_rx")
-            self.comb += [
-                # UART TX.
+        if cpu_type is not None:
+            assert uart_type in ["rs232", "fifo"]
+            if uart_type == "fifo":
+                uart_interface = RS232PHYInterface()
+                self.submodules.uart = UART(uart_interface, tx_fifo_depth=1, rx_fifo_depth=1)
+                uart_tx_pads = platform.request("uart_tx")
+                uart_rx_pads = platform.request("uart_rx")
+                self.comb += [
+                    # UART TX.
                 uart_tx_pads.valid.eq(uart_interface.sink.valid),
-                uart_interface.sink.ready.eq(uart_tx_pads.ready),
-                uart_tx_pads.data.eq(uart_interface.sink.data),
+                    uart_interface.sink.ready.eq(uart_tx_pads.ready),
+                    uart_tx_pads.data.eq(uart_interface.sink.data),
 
                 # UART RX.
                 uart_interface.source.valid.eq(uart_rx_pads.valid),
-                uart_rx_pads.ready.eq(uart_interface.source.ready),
-                uart_interface.source.data.eq(uart_rx_pads.data)
-            ]
-        else:
-            self.submodules.uart_phy = RS232PHY(platform.request("uart"), self.clk_freq, 115200)
-            self.submodules.uart = UART(self.uart_phy)
-        if self.irq.enabled:
-            self.irq.add("uart", use_loc_if_exists=True)
-        else:
-            self.add_constant("UART_POLLING")
+                    uart_rx_pads.ready.eq(uart_interface.source.ready),
+                    uart_interface.source.data.eq(uart_rx_pads.data)
+                ]
+            else:
+                self.submodules.uart_phy = RS232PHY(platform.request("uart"), self.clk_freq, 115200)
+                self.submodules.uart = UART(self.uart_phy)
+            if self.irq.enabled:
+                self.irq.add("uart", use_loc_if_exists=True)
+            else:
+                self.add_constant("UART_POLLING")
 
         # CRG --------------------------------------------------------------------------------------
         if isinstance(platform, SimPlatform):