From 50e1d478db66570d68316525ecb37bfc434f25c3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 May 2019 15:44:44 +0200 Subject: [PATCH] PhySettings: add databits to allow SoC to compute memory size more easily --- litedram/common.py | 2 +- litedram/phy/ecp5ddrphy.py | 1 + litedram/phy/gensdrphy.py | 1 + litedram/phy/s6ddrphy.py | 2 ++ litedram/phy/s7ddrphy.py | 1 + litedram/phy/usddrphy.py | 1 + 6 files changed, 7 insertions(+), 1 deletion(-) diff --git a/litedram/common.py b/litedram/common.py index db33f17..879bd34 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -21,7 +21,7 @@ class Settings: class PhySettings(Settings): - def __init__(self, memtype, dfi_databits, + def __init__(self, memtype, databits, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py index b21fc80..10bf6ab 100644 --- a/litedram/phy/ecp5ddrphy.py +++ b/litedram/phy/ecp5ddrphy.py @@ -138,6 +138,7 @@ class ECP5DDRPHY(Module, AutoCSR): wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl) self.settings = PhySettings( memtype=memtype, + databits=databits, dfi_databits=4*databits, nranks=nranks, nphases=nphases, diff --git a/litedram/phy/gensdrphy.py b/litedram/phy/gensdrphy.py index fd7509f..ae5542f 100644 --- a/litedram/phy/gensdrphy.py +++ b/litedram/phy/gensdrphy.py @@ -31,6 +31,7 @@ class GENSDRPHY(Module): self.settings = PhySettings( memtype="SDR", + databits=databits, dfi_databits=databits, nranks=nranks, nphases=1, diff --git a/litedram/phy/s6ddrphy.py b/litedram/phy/s6ddrphy.py index ff11f3f..67829c3 100644 --- a/litedram/phy/s6ddrphy.py +++ b/litedram/phy/s6ddrphy.py @@ -43,6 +43,7 @@ class S6HalfRateDDRPHY(Module): if memtype == "DDR3": self.settings = PhySettings( memtype="DDR3", + databits=databits, dfi_databits=2*databits, nranks=nranks, nphases=nphases, @@ -58,6 +59,7 @@ class S6HalfRateDDRPHY(Module): else: self.settings = PhySettings( memtype=memtype, + databits=databits, dfi_databits=2*databits, nranks=nranks, nphases=nphases, diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index 424c617..68eb131 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -94,6 +94,7 @@ class S7DDRPHY(Module, AutoCSR): wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl) self.settings = PhySettings( memtype=memtype, + databits=databits, dfi_databits=2*databits, nranks=nranks, nphases=nphases, diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py index 6068520..2964656 100644 --- a/litedram/phy/usddrphy.py +++ b/litedram/phy/usddrphy.py @@ -106,6 +106,7 @@ class USDDRPHY(Module, AutoCSR): wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl) self.settings = PhySettings( memtype=memtype, + databits=databits, dfi_databits=2*databits, nranks=nranks, nphases=nphases,