From 53887fcb8e87027f298ccb17f047b0695bd7b023 Mon Sep 17 00:00:00 2001
From: Mark <mstandke@cern.ch>
Date: Mon, 13 Jan 2020 14:05:38 +0100
Subject: [PATCH] ADD: KX2 DDR3 module

---
 litedram/modules.py | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 6145040..349b5b2 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -375,6 +375,19 @@ class K4B2G1646F(SDRAMModule):
     }
     speedgrade_timings["default"] = speedgrade_timings["1600"]
 
+class H5TC4G63CFR(SDRAMModule):
+    memtype = "DDR3"
+    # geometry
+    nbanks = 8
+    nrows  = 16384
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 7.5), tZQCS=(64, 80))
+    speedgrade_timings = {
+        "800":  _SpeedgradeTimings(tRP=15,     tRCD=15,     tWR=15, tRFC=(260, None), tFAW=(None, 40), tRAS=37.5),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["800"]
+
 
 class IS43TR16128B(SDRAMModule):
     memtype = "DDR3"