From 53c75f50c879f1d7869c842c07c310de9a261db8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 22 Aug 2018 12:32:19 +0200 Subject: [PATCH] phy/s7ddrphy: add dqs preamble/postamble --- litedram/phy/s7ddrphy.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index f0b97ab..fbabb67 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -208,6 +208,8 @@ class S7DDRPHY(Module, AutoCSR): # DQS and DM oe_dqs = Signal() + dqs_preamble = Signal() + dqs_postamble = Signal() dqs_serdes_pattern = Signal(8, reset=0b01010101) if with_odelay: self.comb += \ @@ -217,9 +219,20 @@ class S7DDRPHY(Module, AutoCSR): ).Else( dqs_serdes_pattern.eq(0b00000000) ) + ).Elif(dqs_preamble | dqs_postamble, + dqs_serdes_pattern.eq(0b0000000) ).Else( dqs_serdes_pattern.eq(0b01010101) ) + else: + self.comb += [ + If(dqs_preamble | dqs_postamble, + dqs_serdes_pattern.eq(0b0000000) + ).Else( + dqs_serdes_pattern.eq(0b01010101) + ) + ] + for i in range(databits//8): dm_o_nodelay = Signal() self.specials += \ @@ -419,6 +432,14 @@ class S7DDRPHY(Module, AutoCSR): oe_dq.eq(oe) ] + # dqs preamble/postamble + self.comb += [ + dqs_preamble.eq(last_wrdata_en[cwl_sys_latency-1] & + ~last_wrdata_en[cwl_sys_latency]), + dqs_postamble.eq(last_wrdata_en[cwl_sys_latency+1] & + ~last_wrdata_en[cwl_sys_latency]), + ] + class V7DDRPHY(S7DDRPHY): def __init__(self, pads, **kwargs):