From 55b5f40e0031f66b50516bc528e1198d5acb0289 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 8 Nov 2018 16:40:38 +0100
Subject: [PATCH] modules: add AS4C256M16D3A

---
 litedram/modules.py | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 9c0da61..89cd2ac 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -325,6 +325,20 @@ class MT18KSF1G72HZ(SDRAMModule):
     speedgrade_timings["default"] = speedgrade_timings["1600"]
 
 
+class AS4C256M16D3A(SDRAMModule):
+    memtype = "DDR3"
+    # geometry
+    nbanks = 8
+    nrows  = 32768
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 7.5))
+    speedgrade_timings = {
+        "1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=260, tFAW=(None, 40), tRAS=35),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["1600"]
+
+
 # DDR4 (Chips)
 class EDY4016A(SDRAMModule):
     memtype = "DDR4"