From 58235f478e60ce566ca23c0f339eeb4fdb8b302b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <jboczar@antmicro.com>
Date: Fri, 19 Mar 2021 11:34:56 +0100
Subject: [PATCH] lpddr4/init: increase CA/DQ Vref to 30.4% (yields better
 results)

---
 litedram/init.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litedram/init.py b/litedram/init.py
index 0135efe..4b7e8d5 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -583,11 +583,11 @@ def get_lpddr4_phy_init_sequence(phy_settings, timing_settings):
         (4, 3, odt_map[ca_odt]),
     ])
     mr[12] = reg([
-        (0, 6, vref_ranges[1][27.2]),  # Vref(CA) 27.2% VDD2
+        (0, 6, vref_ranges[1][30.4]),  # Vref(CA) % of VDD2
         (6, 1, 1),  # range[1]
     ])
     mr[14] = reg([
-        (0, 6, vref_ranges[1][27.2]),  # Vref(DQ) 27.2% VDDQ
+        (0, 6, vref_ranges[1][30.4]),  # Vref(DQ) % of VDDQ
         (6, 1, 1),  # range[1]
     ])
     mr[13] = 0  # defaults (data mask enabled, frequency set point 0)