From 5f6b85703dbe359d5046b8fe4b9fcabfb5f52fcd Mon Sep 17 00:00:00 2001
From: John Sully <john@LAPTOP-VGQL9KOL.CSQUARE.local>
Date: Sun, 23 Sep 2018 17:56:07 +0200
Subject: [PATCH] This adds support for tRC timing parameters

---
 litedram/common.py           |  3 ++-
 litedram/core/bankmachine.py | 29 +++++++++++++++++++++--------
 litedram/modules.py          |  5 +++++
 3 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/litedram/common.py b/litedram/common.py
index 7513e65..4e4fe46 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -43,7 +43,7 @@ class GeomSettings:
 
 
 class TimingSettings:
-    def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, tFAW, tCCD, tRRD):
+    def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, tFAW, tCCD, tRRD, tRC):
         self.tRP = tRP
         self.tRCD = tRCD
         self.tWR = tWR
@@ -53,6 +53,7 @@ class TimingSettings:
         self.tFAW = tFAW
         self.tCCD = tCCD
         self.tRRD = tRRD
+        self.tRC = tRC
 
 
 def cmd_layout(address_width):
diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py
index 1df3aa6..b4fa9bd 100644
--- a/litedram/core/bankmachine.py
+++ b/litedram/core/bankmachine.py
@@ -89,6 +89,17 @@ class BankMachine(Module):
         self.submodules += precharge_timer
         self.comb += precharge_timer.wait.eq(~(cmd.valid & cmd.ready & cmd.is_write))
 
+        # Respect tRC activate-activate time
+        activate_allowed = Signal()
+        if settings.timing.tRC is not None:
+            trc_time = settings.timing.tRC - 1
+            trc_timer = WaitTimer(trc_time)
+            self.submodules += trc_timer
+            self.comb += trc_timer.wait.eq(~(cmd.valid & cmd.ready & track_open))
+            self.comb += activate_allowed.eq(trc_timer.done)
+        else:
+            self.comb += activate_allowed.eq(1)
+
         # Auto Precharge
         if settings.with_auto_precharge:
             self.comb += [
@@ -151,14 +162,16 @@ class BankMachine(Module):
             track_close.eq(1)
         )
         fsm.act("ACTIVATE",
-            sel_row_addr.eq(1),
-            track_open.eq(1),
-            cmd.valid.eq(ras_allowed),
-            cmd.is_cmd.eq(1),
-            If(cmd.ready & ras_allowed,
-                NextState("TRCD")
-            ),
-            cmd.ras.eq(1)
+            If(activate_allowed,
+                sel_row_addr.eq(1),
+                track_open.eq(1),
+                cmd.valid.eq(ras_allowed),
+                cmd.is_cmd.eq(1),
+                If(cmd.ready & ras_allowed,
+                    NextState("TRCD")
+                ),
+                cmd.ras.eq(1)
+            )
         )
         fsm.act("REFRESH",
             If(precharge_timer.done,
diff --git a/litedram/modules.py b/litedram/modules.py
index f52fe52..6459511 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -35,6 +35,7 @@ class SDRAMModule:
             tFAW=None if self.get("tFAW") is None else self.ck_ns_to_cycles(*self.get("tFAW")),
             tCCD=None if self.get("tCCD") is None else self.ck_ns_to_cycles(*self.get("tCCD")),
             tRRD=None if self.get("tRRD") is None else self.ns_to_cycles_trrd(self.get("tRRD")),
+            tRC=None if self.get("tRC") is None else self.ns_to_cycles(self.get("tRC"))
         )
 
     def get(self, name):
@@ -252,24 +253,28 @@ class MT41J128M16(SDRAMModule):
     tWR_1066  = 13.1
     tRFC_1066 = 86
     tFAW_1066 = (27, None)
+    tRC_1066 = 50.625
     # DDR3-1333
     tRP_1333  = 13.5
     tRCD_1333 = 13.5
     tWR_1333  = 13.5
     tRFC_1333 = 107
     tFAW_1333 = (30, None)
+    tRC_1333 = 49.5
     # DDR3-1600
     tRP_1600  = 13.75
     tRCD_1600 = 13.75
     tWR_1600  = 13.75
     tRFC_1600 = 128
     tFAW_1600 = (32, None)
+    tRC_1600 = 48.75
     # API retro-compatibility
     tRP  = tRP_1600
     tRCD = tRCD_1600
     tWR  = tWR_1600
     tRFC = tRFC_1600
     tFAW = tFAW_1600
+    tRC = tRC_1600
 
 
 class MT41K128M16(MT41J128M16):