diff --git a/litedram/phy/dfi.py b/litedram/phy/dfi.py index 5e87d7c..2948556 100644 --- a/litedram/phy/dfi.py +++ b/litedram/phy/dfi.py @@ -75,3 +75,21 @@ class Interface(Record): class Interconnect(Module): def __init__(self, master, slave): self.comb += master.connect(slave) + + +class DDR4DFIMux(Module): + def __init__(self, dfi_i, dfi_o): + for i in range(len(dfi_i.phases)): + p_i = dfi_i.phases[i] + p_o = dfi_o.phases[i] + self.comb += [ + p_i.connect(p_o), + If(~p_i.ras_n & p_i.cas_n & p_i.we_n, + p_o.act_n.eq(0), + p_o.we_n.eq(p_i.address[14]), + p_o.cas_n.eq(p_i.address[15]), + p_o.ras_n.eq(p_i.address[16]) + ).Else( + p_o.act_n.eq(1), + ) + ] diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py index 47320e5..b57dfbd 100644 --- a/litedram/phy/usddrphy.py +++ b/litedram/phy/usddrphy.py @@ -16,24 +16,6 @@ from litedram.common import * from litedram.phy.dfi import * -class DDR4DFIMux(Module): - def __init__(self, dfi_i, dfi_o): - for i in range(len(dfi_i.phases)): - p_i = dfi_i.phases[i] - p_o = dfi_o.phases[i] - self.comb += [ - p_i.connect(p_o), - If(~p_i.ras_n & p_i.cas_n & p_i.we_n, - p_o.act_n.eq(0), - p_o.we_n.eq(p_i.address[14]), - p_o.cas_n.eq(p_i.address[15]), - p_o.ras_n.eq(p_i.address[16]) - ).Else( - p_o.act_n.eq(1), - ) - ] - - class USDDRPHY(Module, AutoCSR): def __init__(self, pads, memtype="DDR3", sys_clk_freq=100e6, iodelay_clk_freq=200e6, cmd_latency=0): tck = 2/(2*4*sys_clk_freq) @@ -94,13 +76,10 @@ class USDDRPHY(Module, AutoCSR): write_latency=cwl_sys_latency ) - self.dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases) - if memtype == "DDR3": - _dfi = self.dfi - else: - _dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases) - dfi_mux = DDR4DFIMux(self.dfi, _dfi) - self.submodules += dfi_mux + self.dfi = dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases) + if memtype == "DDR4": + dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases) + self.submodules += DDR4DFIMux(self.dfi, dfi) # # # @@ -146,10 +125,10 @@ class USDDRPHY(Module, AutoCSR): o_OQ=a_o_nodelay, i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), - i_D=Cat(_dfi.phases[0].address[i], _dfi.phases[0].address[i], - _dfi.phases[1].address[i], _dfi.phases[1].address[i], - _dfi.phases[2].address[i], _dfi.phases[2].address[i], - _dfi.phases[3].address[i], _dfi.phases[3].address[i]) + i_D=Cat(dfi.phases[0].address[i], dfi.phases[0].address[i], + dfi.phases[1].address[i], dfi.phases[1].address[i], + dfi.phases[2].address[i], dfi.phases[2].address[i], + dfi.phases[3].address[i], dfi.phases[3].address[i]) ), Instance("ODELAYE3", p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6, @@ -180,10 +159,10 @@ class USDDRPHY(Module, AutoCSR): o_OQ=ba_o_nodelay, i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), - i_D=Cat(_dfi.phases[0].bank[i], _dfi.phases[0].bank[i], - _dfi.phases[1].bank[i], _dfi.phases[1].bank[i], - _dfi.phases[2].bank[i], _dfi.phases[2].bank[i], - _dfi.phases[3].bank[i], _dfi.phases[3].bank[i]) + i_D=Cat(dfi.phases[0].bank[i], dfi.phases[0].bank[i], + dfi.phases[1].bank[i], dfi.phases[1].bank[i], + dfi.phases[2].bank[i], dfi.phases[2].bank[i], + dfi.phases[3].bank[i], dfi.phases[3].bank[i]) ), Instance("ODELAYE3", p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6, @@ -215,10 +194,10 @@ class USDDRPHY(Module, AutoCSR): o_OQ=x_o_nodelay, i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), - i_D=Cat(getattr(_dfi.phases[0], name), getattr(_dfi.phases[0], name), - getattr(_dfi.phases[1], name), getattr(_dfi.phases[1], name), - getattr(_dfi.phases[2], name), getattr(_dfi.phases[2], name), - getattr(_dfi.phases[3], name), getattr(_dfi.phases[3], name)) + i_D=Cat(getattr(dfi.phases[0], name), getattr(dfi.phases[0], name), + getattr(dfi.phases[1], name), getattr(dfi.phases[1], name), + getattr(dfi.phases[2], name), getattr(dfi.phases[2], name), + getattr(dfi.phases[3], name), getattr(dfi.phases[3], name)) ), Instance("ODELAYE3", p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6, @@ -256,10 +235,10 @@ class USDDRPHY(Module, AutoCSR): o_OQ=dm_o_nodelay, i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), - i_D=Cat(_dfi.phases[0].wrdata_mask[i], _dfi.phases[0].wrdata_mask[databits//8+i], - _dfi.phases[1].wrdata_mask[i], _dfi.phases[1].wrdata_mask[databits//8+i], - _dfi.phases[2].wrdata_mask[i], _dfi.phases[2].wrdata_mask[databits//8+i], - _dfi.phases[3].wrdata_mask[i], _dfi.phases[3].wrdata_mask[databits//8+i]) + i_D=Cat(dfi.phases[0].wrdata_mask[i], dfi.phases[0].wrdata_mask[databits//8+i], + dfi.phases[1].wrdata_mask[i], dfi.phases[1].wrdata_mask[databits//8+i], + dfi.phases[2].wrdata_mask[i], dfi.phases[2].wrdata_mask[databits//8+i], + dfi.phases[3].wrdata_mask[i], dfi.phases[3].wrdata_mask[databits//8+i]) ) self.specials += \ Instance("ODELAYE3", @@ -350,10 +329,10 @@ class USDDRPHY(Module, AutoCSR): o_OQ=dq_o_nodelay, o_T_OUT=dq_t, i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), - i_D=Cat(_dfi.phases[0].wrdata[i], _dfi.phases[0].wrdata[databits+i], - _dfi.phases[1].wrdata[i], _dfi.phases[1].wrdata[databits+i], - _dfi.phases[2].wrdata[i], _dfi.phases[2].wrdata[databits+i], - _dfi.phases[3].wrdata[i], _dfi.phases[3].wrdata[databits+i]), + i_D=Cat(dfi.phases[0].wrdata[i], dfi.phases[0].wrdata[databits+i], + dfi.phases[1].wrdata[i], dfi.phases[1].wrdata[databits+i], + dfi.phases[2].wrdata[i], dfi.phases[2].wrdata[databits+i], + dfi.phases[3].wrdata[i], dfi.phases[3].wrdata[databits+i]), i_T=~oe_dq ), Instance("ISERDESE3", @@ -400,15 +379,15 @@ class USDDRPHY(Module, AutoCSR): ) ] self.comb += [ - _dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]), - _dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]), - _dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]), - _dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]), + dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]), + dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]), + dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]), + dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]), - _dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]), - _dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]), - _dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]), - _dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7]), + dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]), + dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]), + dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]), + dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7]), ] # Flow control @@ -418,19 +397,19 @@ class USDDRPHY(Module, AutoCSR): # cl_sys_latency cycles CAS # 2 cycles through ISERDESE2 # 3 cycles through Bitslip - rddata_en = _dfi.phases[self.settings.rdphase].rddata_en + rddata_en = dfi.phases[self.settings.rdphase].rddata_en for i in range(self.settings.read_latency-1): n_rddata_en = Signal() self.sync += n_rddata_en.eq(rddata_en) rddata_en = n_rddata_en - for phase in _dfi.phases: + for phase in dfi.phases: phase_rddata_valid = Signal() self.sync += phase_rddata_valid.eq(rddata_en | self._wlevel_en.storage) self.comb += phase.rddata_valid.eq(phase_rddata_valid) oe = Signal() last_wrdata_en = Signal(cwl_sys_latency+2) - wrphase = _dfi.phases[self.settings.wrphase] + wrphase = dfi.phases[self.settings.wrphase] self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:-1])) self.comb += oe.eq( last_wrdata_en[cwl_sys_latency-1] |