From 5a4ed3d2043764aa7684aed240ab09c183f28c25 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 9 Jul 2021 17:58:33 +0200 Subject: [PATCH] bench/arty/kc705: Use PHYPadsReducer to easily test various DFI sizes. --- bench/arty.py | 4 +++- bench/kc705.py | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index 6951d33..c108640 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -18,6 +18,7 @@ from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * +from litedram.common import PHYPadsReducer from litedram.phy import s7ddrphy from litedram.modules import MT41K128M16 @@ -82,7 +83,8 @@ class BenchSoC(SoCCore): self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- - self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), + self.submodules.ddrphy = s7ddrphy.A7DDRPHY( + pads = PHYPadsReducer(platform.request("ddram"), [0, 1]), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) diff --git a/bench/kc705.py b/bench/kc705.py index f7383ab..c8c8764 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -18,6 +18,7 @@ from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * +from litedram.common import PHYPadsReducer from litedram.phy import s7ddrphy from litedram.modules import MT8JTF12864 @@ -75,7 +76,8 @@ class BenchSoC(SoCCore): self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- - self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), + self.submodules.ddrphy = s7ddrphy.K7DDRPHY( + pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq)