From 5aad6cd3d1ace3298ad3eb4d431a22f56578638e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= <jf@lambdaconcept.com>
Date: Tue, 3 Aug 2021 16:41:45 +0200
Subject: [PATCH] gen: use sys_clk_freq for SDRAMPHYModel timings, instead of
 100MHz.

---
 litedram/gen.py | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/litedram/gen.py b/litedram/gen.py
index e1de734..dc0225e 100755
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -557,15 +557,14 @@ class LiteDRAMCore(SoCCore):
         # Sim.
         if isinstance(platform, SimPlatform):
             from litex.tools.litex_sim import get_sdram_phy_settings
-            sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
             phy_settings   = get_sdram_phy_settings(
                 memtype    = sdram_module.memtype,
                 data_width = core_config["sdram_module_nb"]*8,
-                clk_freq   = sdram_clk_freq)
+                clk_freq   = sys_clk_freq)
             self.submodules.ddrphy = sdram_phy = SDRAMPHYModel(
                 module    = sdram_module,
                 settings  = phy_settings,
-                clk_freq  = sdram_clk_freq)
+                clk_freq  = sys_clk_freq)
 
         # GENSDRPHY.
         elif core_config["sdram_phy"] in [litedram_phys.GENSDRPHY]: