From 5b02791580db9d1bae64b6524b7aca3540d89937 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 2 Oct 2018 08:41:48 +0200
Subject: [PATCH] modules: add tCCD to all modules

---
 litedram/modules.py | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/litedram/modules.py b/litedram/modules.py
index 8821ad5..12d6643 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -93,14 +93,14 @@ class IS42S16160(SDRAMModule):
     nrows  = 8192
     ncols  = 512
     # speedgrade invariant timings
+    tREFI = 64e6/8192
+    tWTR = (2, None)
+    tCCD = (1, None)
+    # speedgrade related timings
     tRP   = 20
     tRCD  = 20
     tWR   = 20
-    tREFI = 64e6/8192
     tRFC  = 70
-    # speedgrade related timings
-    tWTR = (2, None)
-
 
 class MT48LC4M16(SDRAMModule):
     memtype = "SDR"
@@ -111,6 +111,7 @@ class MT48LC4M16(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/4096
     tWTR = (2, None)
+    tCCD = (1, None)
     # speedgrade related timings
     tRP   = 15
     tRCD  = 15
@@ -127,6 +128,7 @@ class AS4C16M16(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR = (2, None)
+    tCCD = (1, None)
     # speedgrade related timings
     tRP   = 18
     tRCD  = 18
@@ -144,6 +146,7 @@ class MT46V32M16(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR = (2, None)
+    tCCD = (1, None)
     # speedgrade related timings
     tRP   = 15
     tRCD  = 15
@@ -161,6 +164,7 @@ class MT46H32M16(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR = (2, None)
+    tCCD = (1, None)
     # speedgrade related timings
     tRP   = 15
     tRCD  = 15
@@ -176,7 +180,8 @@ class MT46H32M32(SDRAMModule):
     ncols  = 1024
     # speedgrade invariant timings
     tREFI = 64e6/8192
-    tWTR = (2, None)
+    tWTR = (1, None)
+    tCCD = (1, None)
     # speedgrade related timings
     tRP   = 15
     tRCD  = 15