From 8226dca89803015ac95edb08d93980f0aefe3d92 Mon Sep 17 00:00:00 2001
From: Christian Klarhorst <cklarhor@techfak.uni-bielefeld.de>
Date: Thu, 25 Nov 2021 14:18:05 +0100
Subject: [PATCH] add LPDDR module

---
 litedram/modules.py | 10 ++++++++++
 1 file changed, 10 insertions(+)
 mode change 100644 => 100755 litedram/modules.py

diff --git a/litedram/modules.py b/litedram/modules.py
old mode 100644
new mode 100755
index b46aaf5..7115698
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -572,6 +572,16 @@ class MT46H32M16(LPDDRModule):
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
 
+class MT46H64M16(LPDDRModule):
+    # geometry
+    nbanks = 4
+    nrows  = 16384
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
+
+
 class MT46H32M32(LPDDRModule):
     # geometry
     nbanks = 4