From 5cd192a70888c6f08b163ddbdf03403797a911bb Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 30 Mar 2021 08:49:54 +0200
Subject: [PATCH] bench: Remove soc_sdram import (No longer useful and
 deprecated).

---
 bench/arty.py     | 1 -
 bench/genesys2.py | 1 -
 bench/kc705.py    | 1 -
 bench/kcu105.py   | 1 -
 bench/xcu1525.py  | 1 -
 5 files changed, 5 deletions(-)

diff --git a/bench/arty.py b/bench/arty.py
index eac4018..e44bbc1 100755
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -16,7 +16,6 @@ from litex_boards.platforms import arty
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
 from litex.soc.integration.soc_core import *
-from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.phy import s7ddrphy
diff --git a/bench/genesys2.py b/bench/genesys2.py
index 9b0a3c0..db79364 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -16,7 +16,6 @@ from litex_boards.platforms import genesys2
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
 from litex.soc.integration.soc_core import *
-from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.phy import s7ddrphy
diff --git a/bench/kc705.py b/bench/kc705.py
index f59854e..e465b9e 100755
--- a/bench/kc705.py
+++ b/bench/kc705.py
@@ -16,7 +16,6 @@ from litex_boards.platforms import kc705
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
 from litex.soc.integration.soc_core import *
-from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.phy import s7ddrphy
diff --git a/bench/kcu105.py b/bench/kcu105.py
index a27d763..5902518 100755
--- a/bench/kcu105.py
+++ b/bench/kcu105.py
@@ -17,7 +17,6 @@ from litex_boards.platforms import kcu105
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
 from litex.soc.integration.soc_core import *
-from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import EDY4016A
diff --git a/bench/xcu1525.py b/bench/xcu1525.py
index 1fcbb47..f8d6598 100755
--- a/bench/xcu1525.py
+++ b/bench/xcu1525.py
@@ -17,7 +17,6 @@ from litex_boards.platforms import xcu1525
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
 from litex.soc.integration.soc_core import *
-from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT40A512M8