diff --git a/bench/arty.py b/bench/arty.py
index 577d8b4..8f0277a 100755
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -82,18 +82,12 @@ class BenchSoC(SoCCore):
             sys_clk_freq = sys_clk_freq)
         self.add_csr("ddrphy")
         self.add_sdram("sdram",
-            phy    = self.ddrphy,
-            module = MT41K128M16(sys_clk_freq, "1:4"),
-            origin = self.mem_map["main_ram"]
+            phy       = self.ddrphy,
+            module    = MT41K128M16(sys_clk_freq, "1:4"),
+            origin    = self.mem_map["main_ram"],
+            with_bist = with_bist,
         )
 
-        # BIST -------------------------------------------------------------------------------------
-        from litedram.frontend.bist import  LiteDRAMBISTGenerator, LiteDRAMBISTChecker
-        self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_generator")
-        self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_checker")
-
         # UARTBone ---------------------------------------------------------------------------------
         if uart != "serial":
             self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
diff --git a/bench/genesys2.py b/bench/genesys2.py
index 9816a1c..c853cee 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -80,18 +80,12 @@ class BenchSoC(SoCCore):
             sys_clk_freq = sys_clk_freq)
         self.add_csr("ddrphy")
         self.add_sdram("sdram",
-            phy    = self.ddrphy,
-            module = MT41J256M16(sys_clk_freq, "1:4"),
-            origin = self.mem_map["main_ram"]
+            phy       = self.ddrphy,
+            module    = MT41J256M16(sys_clk_freq, "1:4"),
+            origin    = self.mem_map["main_ram"],
+            with_bist = with_bist,
         )
 
-        # BIST -------------------------------------------------------------------------------------
-        from litedram.frontend.bist import  LiteDRAMBISTGenerator, LiteDRAMBISTChecker
-        self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_generator")
-        self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_checker")
-
         # UARTBone ---------------------------------------------------------------------------------
         if uart != "serial":
             self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
diff --git a/bench/kc705.py b/bench/kc705.py
index 4214d61..649b7b7 100755
--- a/bench/kc705.py
+++ b/bench/kc705.py
@@ -80,18 +80,12 @@ class BenchSoC(SoCCore):
             sys_clk_freq = sys_clk_freq)
         self.add_csr("ddrphy")
         self.add_sdram("sdram",
-            phy    = self.ddrphy,
-            module = MT8JTF12864(sys_clk_freq, "1:4"),
-            origin = self.mem_map["main_ram"]
+            phy       = self.ddrphy,
+            module    = MT8JTF12864(sys_clk_freq, "1:4"),
+            origin    = self.mem_map["main_ram"],
+            with_bist = with_bist,
         )
 
-        # BIST -------------------------------------------------------------------------------------
-        from litedram.frontend.bist import  LiteDRAMBISTGenerator, LiteDRAMBISTChecker
-        self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_generator")
-        self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_checker")
-
         # UARTBone ---------------------------------------------------------------------------------
         if uart != "serial":
             self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
diff --git a/bench/kcu105.py b/bench/kcu105.py
index d6640c3..8ab8713 100755
--- a/bench/kcu105.py
+++ b/bench/kcu105.py
@@ -92,19 +92,13 @@ class BenchSoC(SoCCore):
             iodelay_clk_freq = 200e6)
         self.add_csr("ddrphy")
         self.add_sdram("sdram",
-            phy    = self.ddrphy,
-            module = EDY4016A(sys_clk_freq, "1:4"),
-            origin = self.mem_map["main_ram"],
-            size   = 0x40000000,
+            phy       = self.ddrphy,
+            module    = EDY4016A(sys_clk_freq, "1:4"),
+            origin    = self.mem_map["main_ram"],
+            size      = 0x40000000,
+            with_bist = with_bist,
         )
 
-        # BIST -------------------------------------------------------------------------------------
-        from litedram.frontend.bist import  LiteDRAMBISTGenerator, LiteDRAMBISTChecker
-        self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_generator")
-        self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_checker")
-
         # UARTBone ---------------------------------------------------------------------------------
         if uart != "serial":
             self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
diff --git a/bench/xcu1525.py b/bench/xcu1525.py
index fc59325..c49a99e 100755
--- a/bench/xcu1525.py
+++ b/bench/xcu1525.py
@@ -88,21 +88,15 @@ class BenchSoC(SoCCore):
             iodelay_clk_freq = 500e6)
         self.add_csr("ddrphy")
         self.add_sdram("sdram",
-            phy    = self.ddrphy,
-            module = MT40A512M8(sys_clk_freq, "1:4"),
-            origin = self.mem_map["main_ram"],
-            size   = 0x40000000,
+            phy       = self.ddrphy,
+            module    = MT40A512M8(sys_clk_freq, "1:4"),
+            origin    = self.mem_map["main_ram"],
+            size      = 0x40000000,
+            with_bist = with_bist,
         )
         # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
         platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")
 
-        # BIST -------------------------------------------------------------------------------------
-        from litedram.frontend.bist import  LiteDRAMBISTGenerator, LiteDRAMBISTChecker
-        self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_generator")
-        self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
-        self.add_csr("sdram_checker")
-
         # UARTBone ---------------------------------------------------------------------------------
         if uart != "serial":
             self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")