From 5d1a9847aa805034e58eabf376e2807bfed7b133 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 29 Sep 2019 14:42:41 +0200 Subject: [PATCH] core: add LiteDRAMCore (ControllerInjector from LiteX) --- litedram/core/__init__.py | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/litedram/core/__init__.py b/litedram/core/__init__.py index 4a28b54..86aaac6 100644 --- a/litedram/core/__init__.py +++ b/litedram/core/__init__.py @@ -1,2 +1,29 @@ +from migen import * + +from litex.soc.interconnect.csr import AutoCSR + +from litedram.dfii import DFIInjector from litedram.core.controller import ControllerSettings, LiteDRAMController -from litedram.core.crossbar import LiteDRAMCrossbar \ No newline at end of file +from litedram.core.crossbar import LiteDRAMCrossbar + +# Core --------------------------------------------------------------------------------------------- + +class LiteDRAMCore(Module, AutoCSR): + def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs): + self.submodules.dfii = DFIInjector( + addressbits = geom_settings.addressbits, + bankbits = geom_settings.bankbits, + nranks = phy.settings.nranks, + databits = phy.settings.dfi_databits, + nphases = phy.settings.nphases) + self.comb += self.dfii.master.connect(phy.dfi) + + self.submodules.controller = controller = LiteDRAMController( + phy_settings = phy.settings, + geom_settings = geom_settings, + timing_settings = timing_settings, + clk_freq = clk_freq, + **kwargs) + self.comb += controller.dfi.connect(self.dfii.slave) + + self.submodules.crossbar = LiteDRAMCrossbar(controller.interface)