From 5f722a1513c887bcd07230df9bf3918c46ec9e4a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 15 Feb 2022 17:33:31 +0100 Subject: [PATCH] bench/test: Avoid use of ident_version (should fix CI). --- bench/arty.py | 1 - bench/genesys2.py | 1 - bench/kc705.py | 1 - bench/kcu105.py | 1 - bench/xcu1525.py | 1 - litedram/phy/lpddr4/simsoc.py | 1 - litedram/phy/lpddr5/simsoc.py | 7 +++---- litedram/phy/rpc/simsoc.py | 5 ++--- 8 files changed, 5 insertions(+), 13 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index c108640..00f18ed 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -74,7 +74,6 @@ class BenchSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident = "LiteDRAM bench on Arty", - ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", uart_name = uart) diff --git a/bench/genesys2.py b/bench/genesys2.py index 42de20d..c1e2ba7 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -66,7 +66,6 @@ class BenchSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident = "LiteDRAM bench on Genesys2", - ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", uart_name = uart) diff --git a/bench/kc705.py b/bench/kc705.py index c8c8764..68baf41 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -67,7 +67,6 @@ class BenchSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident = "LiteDRAM bench on KC705", - ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", uart_name = uart) diff --git a/bench/kcu105.py b/bench/kcu105.py index 659f91a..79291a2 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -83,7 +83,6 @@ class BenchSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident = "LiteDRAM bench on KCU105", - ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", uart_name = uart) diff --git a/bench/xcu1525.py b/bench/xcu1525.py index 710801e..4c51d96 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -79,7 +79,6 @@ class BenchSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident = "LiteDRAM bench on XCU1525", - ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", uart_name = uart) diff --git a/litedram/phy/lpddr4/simsoc.py b/litedram/phy/lpddr4/simsoc.py index d500c17..f294758 100644 --- a/litedram/phy/lpddr4/simsoc.py +++ b/litedram/phy/lpddr4/simsoc.py @@ -76,7 +76,6 @@ class SimSoC(SoCCore): super().__init__(platform, clk_freq = sys_clk_freq, ident = "LiteX Simulation", - ident_version = True, cpu_variant = "lite", **kwargs) diff --git a/litedram/phy/lpddr5/simsoc.py b/litedram/phy/lpddr5/simsoc.py index 0bb44dd..1a8a0a2 100644 --- a/litedram/phy/lpddr5/simsoc.py +++ b/litedram/phy/lpddr5/simsoc.py @@ -94,10 +94,9 @@ class SimSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- super().__init__(platform, - clk_freq = sys_clk_freq, - ident = "LiteX Simulation", - ident_version = True, - cpu_variant = "lite", + clk_freq = sys_clk_freq, + ident = "LiteX Simulation", + cpu_variant = "lite", **kwargs) # CRG -------------------------------------------------------------------------------------- diff --git a/litedram/phy/rpc/simsoc.py b/litedram/phy/rpc/simsoc.py index d52a5b0..6ddfb76 100644 --- a/litedram/phy/rpc/simsoc.py +++ b/litedram/phy/rpc/simsoc.py @@ -149,9 +149,8 @@ class SimSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, - ident = "LiteX Simulation", - ident_version = True, - cpu_variant = "lite", + ident = "LiteX Simulation", + cpu_variant = "lite", **kwargs) # CRG --------------------------------------------------------------------------------------