diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py
index 2f3675e..6e6e5f5 100644
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@@ -406,7 +406,10 @@ class S7DDRPHY(Module, AutoCSR):
             ]
 
         # dqs preamble/postamble
-        dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency
+        if memtype == "DDR2":
+            dqs_sys_latency = cwl_sys_latency-1
+        elif memtype == "DDR3":
+            dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency
         self.comb += [
             dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] &
                             ~last_wrdata_en[dqs_sys_latency]),