From 6017e7a7635793ad0b22329b5cad7b6ce6002d62 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Sep 2018 12:21:04 +0200 Subject: [PATCH] phy/s7ddrphy: fix dqs_sys_latency for DDR2 --- litedram/phy/s7ddrphy.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index 2f3675e..6e6e5f5 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -406,7 +406,10 @@ class S7DDRPHY(Module, AutoCSR): ] # dqs preamble/postamble - dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency + if memtype == "DDR2": + dqs_sys_latency = cwl_sys_latency-1 + elif memtype == "DDR3": + dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency self.comb += [ dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] & ~last_wrdata_en[dqs_sys_latency]),