From 602ff8be81cc23ea8cb522d3a6cc446d6f455ace Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Aug 2019 07:08:10 +0200 Subject: [PATCH] examples: switch to YAML config files --- examples/{arty_config.py => arty.yml} | 17 ++++++------- examples/{genesys2_config.py => genesys2.yml} | 17 ++++++------- examples/litedram_gen.py | 24 ++++++++++++++----- .../{nexys4ddr_config.py => nexys4ddr.yml} | 17 ++++++------- test/test_examples.py | 2 +- 5 files changed, 40 insertions(+), 37 deletions(-) rename examples/{arty_config.py => arty.yml} (75%) rename examples/{genesys2_config.py => genesys2.yml} (75%) rename examples/{nexys4ddr_config.py => nexys4ddr.yml} (72%) diff --git a/examples/arty_config.py b/examples/arty.yml similarity index 75% rename from examples/arty_config.py rename to examples/arty.yml index fe93d40..f639d67 100644 --- a/examples/arty_config.py +++ b/examples/arty.yml @@ -1,22 +1,19 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD -from litedram.modules import MT41K128M16 -from litedram.phy import A7DDRPHY - -core_config = { +{ # General ------------------------------------------------------------------ "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) - "cmd_latency": 0, # Command additional latency - "sdram_module": MT41K128M16, # SDRAM modules of the board or SO-DIMM - "sdram_module_nb": 2, # Number of byte groups - "sdram_rank_nb": 1, # Number of ranks - "sdram_phy": A7DDRPHY, # Type of FPGA PHY + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "A7DDRPHY", # Type of FPGA PHY # Electrical --------------------------------------------------------------- "rtt_nom": "60ohm", # Nominal termination diff --git a/examples/genesys2_config.py b/examples/genesys2.yml similarity index 75% rename from examples/genesys2_config.py rename to examples/genesys2.yml index 20e6b9f..1b648d5 100644 --- a/examples/genesys2_config.py +++ b/examples/genesys2.yml @@ -1,22 +1,19 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD -from litedram.modules import MT41J256M16 -from litedram.phy import K7DDRPHY - -core_config = { +{ # General ------------------------------------------------------------------ "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -2, # FPGA speedgrade "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) - "cmd_latency": 0, # Command additional latency - "sdram_module": MT41J256M16, # SDRAM modules of the board or SO-DIMM - "sdram_module_nb": 4, # Number of byte groups - "sdram_rank_nb": 1, # Number of ranks - "sdram_phy": K7DDRPHY, # Type of FPGA PHY + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT41J256M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 4, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": K7DDRPHY, # Type of FPGA PHY # Electrical --------------------------------------------------------------- "rtt_nom": "60ohm", # Nominal termination diff --git a/examples/litedram_gen.py b/examples/litedram_gen.py index fee4055..8e33030 100755 --- a/examples/litedram_gen.py +++ b/examples/litedram_gen.py @@ -6,6 +6,7 @@ import os import sys import math import struct +import yaml from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer @@ -14,12 +15,14 @@ from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform from litex.soc.cores.clock import * -from litedram.core.controller import ControllerSettings from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.interconnect import csr_bus from litex.soc.cores.uart import * +from litedram import modules as litedram_modules +from litedram import phy as litedram_phys +from litedram.core.controller import ControllerSettings from litedram.frontend.axi import * from litedram.frontend.bist import LiteDRAMBISTGenerator from litedram.frontend.bist import LiteDRAMBISTChecker @@ -351,19 +354,28 @@ class LiteDRAMCore(SoCSDRAM): def main(): - # get config + # Import YAML config file if len(sys.argv) < 2: - print("missing config file") + print("missing YAML config file") exit(1) - exec(open(sys.argv[1]).read(), globals()) + core_config = yaml.load(open(sys.argv[1]).read(), Loader=yaml.Loader) - # generate core + # Convert YAML elements to Python/LiteX + for k, v in core_config.items(): + if "clk_freq" in k: + core_config[k] = float(core_config[k]) + if k == "sdram_module": + core_config[k] = getattr(litedram_modules, core_config[k]) + if k == "sdram_phy": + core_config[k] = getattr(litedram_phys, core_config[k]) + + # Generate core platform = Platform() soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000) builder = Builder(soc, output_dir="build", compile_gateware=False) vns = builder.build(build_name="litedram_core", regular_comb=False) - # prepare core (could be improved) + # Prepare core (could be improved) def replace_in_file(filename, _from, _to): # Read in the file with open(filename, "r") as file : diff --git a/examples/nexys4ddr_config.py b/examples/nexys4ddr.yml similarity index 72% rename from examples/nexys4ddr_config.py rename to examples/nexys4ddr.yml index fadb142..e588c93 100644 --- a/examples/nexys4ddr_config.py +++ b/examples/nexys4ddr.yml @@ -1,22 +1,19 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD -from litedram.modules import MT47H64M16 -from litedram.phy import A7DDRPHY - -core_config = { +{ # General ------------------------------------------------------------------ "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -1, # FPGA speedgrade "memtype": "DDR2", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_delay": 0, # Command additional delay (in taps) - "cmd_latency": 0, # Command additional latency - "sdram_module": MT47H64M16, # SDRAM modules of the board or SO-DIMM - "sdram_module_nb": 2, # Number of byte groups - "sdram_rank_nb": 1, # Number of ranks - "sdram_phy": A7DDRPHY, # Type of FPGA PHY + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT47H64M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "A7DDRPHY", # Type of FPGA PHY # Frequency ---------------------------------------------------------------- "input_clk_freq": 100e6, # Input clock frequency diff --git a/test/test_examples.py b/test/test_examples.py index c325842..f021d52 100644 --- a/test/test_examples.py +++ b/test/test_examples.py @@ -8,7 +8,7 @@ import os def build_config(name): errors = 0 os.system("rm -rf examples/build") - os.system("cd examples && python3 litedram_gen.py {}_config.py".format(name)) + os.system("cd examples && python3 litedram_gen.py {}.yml".format(name)) errors += not os.path.isfile("examples/build/gateware/litedram_core.v") os.system("rm -rf examples/build") return errors