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examples: switch to YAML config files

This commit is contained in:
Florent Kermarrec 2019-08-28 07:08:10 +02:00
parent fb28f791c8
commit 602ff8be81
5 changed files with 40 additions and 37 deletions
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9
examples/arty_config.py → examples/arty.yml
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@ -1,10 +1,7 @@
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litedram.modules import MT41K128M16
from litedram.phy import A7DDRPHY
core_config = {
{
# General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -1, # FPGA speedgrade
@ -13,10 +10,10 @@ core_config = {
# PHY ----------------------------------------------------------------------
"cmd_delay": 0, # Command additional delay (in taps)
"cmd_latency": 0, # Command additional latency
"sdram_module": MT41K128M16, # SDRAM modules of the board or SO-DIMM
"sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM
"sdram_module_nb": 2, # Number of byte groups
"sdram_rank_nb": 1, # Number of ranks
"sdram_phy": A7DDRPHY, # Type of FPGA PHY
"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
# Electrical ---------------------------------------------------------------
"rtt_nom": "60ohm", # Nominal termination

7
examples/genesys2_config.py → examples/genesys2.yml
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@ -1,10 +1,7 @@
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litedram.modules import MT41J256M16
from litedram.phy import K7DDRPHY
core_config = {
{
# General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -2, # FPGA speedgrade
@ -13,7 +10,7 @@ core_config = {
# PHY ----------------------------------------------------------------------
"cmd_delay": 0, # Command additional delay (in taps)
"cmd_latency": 0, # Command additional latency
"sdram_module": MT41J256M16, # SDRAM modules of the board or SO-DIMM
"sdram_module": "MT41J256M16", # SDRAM modules of the board or SO-DIMM
"sdram_module_nb": 4, # Number of byte groups
"sdram_rank_nb": 1, # Number of ranks
"sdram_phy": K7DDRPHY, # Type of FPGA PHY

24
examples/litedram_gen.py
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@ -6,6 +6,7 @@ import os
import sys
import math
import struct
import yaml
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
@ -14,12 +15,14 @@ from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.soc.cores.clock import *
from litedram.core.controller import ControllerSettings
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.interconnect import csr_bus
from litex.soc.cores.uart import *
from litedram import modules as litedram_modules
from litedram import phy as litedram_phys
from litedram.core.controller import ControllerSettings
from litedram.frontend.axi import *
from litedram.frontend.bist import LiteDRAMBISTGenerator
from litedram.frontend.bist import LiteDRAMBISTChecker
@ -351,19 +354,28 @@ class LiteDRAMCore(SoCSDRAM):
def main():
# get config
# Import YAML config file
if len(sys.argv) < 2:
print("missing config file")
print("missing YAML config file")
exit(1)
exec(open(sys.argv[1]).read(), globals())
core_config = yaml.load(open(sys.argv[1]).read(), Loader=yaml.Loader)
# generate core
# Convert YAML elements to Python/LiteX
for k, v in core_config.items():
if "clk_freq" in k:
core_config[k] = float(core_config[k])
if k == "sdram_module":
core_config[k] = getattr(litedram_modules, core_config[k])
if k == "sdram_phy":
core_config[k] = getattr(litedram_phys, core_config[k])
# Generate core
platform = Platform()
soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000)
builder = Builder(soc, output_dir="build", compile_gateware=False)
vns = builder.build(build_name="litedram_core", regular_comb=False)
# prepare core (could be improved)
# Prepare core (could be improved)
def replace_in_file(filename, _from, _to):
# Read in the file
with open(filename, "r") as file :

9
examples/nexys4ddr_config.py → examples/nexys4ddr.yml
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@ -1,10 +1,7 @@
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litedram.modules import MT47H64M16
from litedram.phy import A7DDRPHY
core_config = {
{
# General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -1, # FPGA speedgrade
@ -13,10 +10,10 @@ core_config = {
# PHY ----------------------------------------------------------------------
"cmd_delay": 0, # Command additional delay (in taps)
"cmd_latency": 0, # Command additional latency
"sdram_module": MT47H64M16, # SDRAM modules of the board or SO-DIMM
"sdram_module": "MT47H64M16", # SDRAM modules of the board or SO-DIMM
"sdram_module_nb": 2, # Number of byte groups
"sdram_rank_nb": 1, # Number of ranks
"sdram_phy": A7DDRPHY, # Type of FPGA PHY
"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
# Frequency ----------------------------------------------------------------
"input_clk_freq": 100e6, # Input clock frequency

2
test/test_examples.py
View File

@ -8,7 +8,7 @@ import os
def build_config(name):
errors = 0
os.system("rm -rf examples/build")
os.system("cd examples && python3 litedram_gen.py {}_config.py".format(name))
os.system("cd examples && python3 litedram_gen.py {}.yml".format(name))
errors += not os.path.isfile("examples/build/gateware/litedram_core.v")
os.system("rm -rf examples/build")
return errors