From 6105ae371e14b43ac1d8b0073f0814ec9f4f4cdc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 Jan 2020 10:48:01 +0100 Subject: [PATCH] modules: be sure tRFC use tuple on all modules --- litedram/modules.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litedram/modules.py b/litedram/modules.py index 74b7639..57aaf27 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -430,9 +430,9 @@ class MT8KTF51264(SDRAMModule): # timings technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10), tZQCS=(64, 80)) speedgrade_timings = { - "800": _SpeedgradeTimings(tRP=13.91, tRCD=13.91, tWR=13.91, tRFC=260, tFAW=(None, 50), tRAS=None), - "1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=86, tFAW=(None, 50), tRAS=None), - "1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=107, tFAW=(None, 45), tRAS=None), + "800": _SpeedgradeTimings(tRP=13.91, tRCD=13.91, tWR=13.91, tRFC=(260, None), tFAW=(None, 50), tRAS=None), + "1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(86, None), tFAW=(None, 50), tRAS=None), + "1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(107, None), tFAW=(None, 45), tRAS=None), } speedgrade_timings["default"] = speedgrade_timings["1333"] @@ -448,7 +448,7 @@ class MT18KSF1G72HZ(SDRAMModule): speedgrade_timings = { "1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(86, None), tFAW=(None, 50), tRAS=None), "1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(107, None), tFAW=(None, 45), tRAS=None), - "1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=(13.125, None), tRFC=128, tFAW=(None, 40), tRAS=None), + "1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=(13.125, None), tRFC=(128, None), tFAW=(None, 40), tRAS=None), } speedgrade_timings["default"] = speedgrade_timings["1600"]