From 2d5a66f6442d973c1c94d1578c64eef845e48f6b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Fin=20Maa=C3=9F?= <f.maass@vogl-electronic.com>
Date: Thu, 13 Jun 2024 12:09:48 +0200
Subject: [PATCH] modules: add Insignis NDS36PT5
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add Insignis NDS36PT5.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
---
 litedram/modules.py | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index f80de56..cfe10d2 100755
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -544,6 +544,15 @@ class M12L16161A(SDRModule):
     technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
 
+class NDS36PT5(SDRModule):
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 512
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(2, 10))
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=10, tRFC=(None, 55), tFAW=None, tRAS=40)}
+
 class W9825G6KH6(SDRModule):
     # geometry
     nbanks = 4