From 6256031d51ccfe817b4e5b6e77207d43d7fe19f0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 22 Apr 2021 14:57:13 +0200 Subject: [PATCH] bench: Update build directories and add rst in CRG (triggered on CPU reboot). --- bench/arty.py | 5 +++-- bench/genesys2.py | 5 +++-- bench/kc705.py | 5 +++-- bench/kcu105.py | 5 +++-- bench/xcu1525.py | 3 ++- 5 files changed, 14 insertions(+), 9 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index 07f9d00..5968d44 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -27,6 +27,7 @@ from liteeth.phy.mii import LiteEthPHYMII class _CRG(Module, AutoCSR): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.clock_domains.cd_sys_pll = ClockDomain() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -50,7 +51,7 @@ class _CRG(Module, AutoCSR): self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk) self.submodules.pll = pll = S7PLL(speedgrade=-1) - self.comb += pll.reset.eq(~main_pll.locked) + self.comb += pll.reset.eq(~main_pll.locked | self.rst) pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) @@ -130,7 +131,7 @@ def main(): args = parser.parse_args() soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer) - builder = Builder(soc, csr_csv="csr.csv") + builder = Builder(soc, output_dir="build/arty", csr_csv="csr.csv") builder.build(run=args.build) if args.load: diff --git a/bench/genesys2.py b/bench/genesys2.py index e8dd14f..20f5030 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -27,6 +27,7 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII class _CRG(Module, AutoCSR): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.clock_domains.cd_sys_pll = ClockDomain() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -45,7 +46,7 @@ class _CRG(Module, AutoCSR): self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.pll = pll = S7PLL(speedgrade=-2) - self.comb += pll.reset.eq(~main_pll.locked) + self.comb += pll.reset.eq(~main_pll.locked | self.rst) pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) @@ -124,7 +125,7 @@ def main(): args = parser.parse_args() soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer) - builder = Builder(soc, csr_csv="csr.csv") + builder = Builder(soc, output_dir="build/genesys2", csr_csv="csr.csv") builder.build(run=args.build) if args.load: diff --git a/bench/kc705.py b/bench/kc705.py index 8b6f281..3dd0625 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -27,6 +27,7 @@ from liteeth.phy import LiteEthPHY class _CRG(Module, AutoCSR): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.clock_domains.cd_sys_pll = ClockDomain() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -45,7 +46,7 @@ class _CRG(Module, AutoCSR): self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.pll = pll = S7PLL(speedgrade=-2) - self.comb += pll.reset.eq(~main_pll.locked) + self.comb += pll.reset.eq(~main_pll.locked | self.rst) pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) @@ -124,7 +125,7 @@ def main(): args = parser.parse_args() soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer) - builder = Builder(soc, csr_csv="csr.csv") + builder = Builder(soc, output_dir="build/kc705", csr_csv="csr.csv") builder.build(run=args.build) if args.load: diff --git a/bench/kcu105.py b/bench/kcu105.py index 71af9f5..2b505ab 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -28,6 +28,7 @@ from liteeth.phy.ku_1000basex import KU_1000BASEX class _CRG(Module, AutoCSR): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.clock_domains.cd_sys_pll = ClockDomain() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -48,7 +49,7 @@ class _CRG(Module, AutoCSR): main_pll.expose_drp() self.submodules.pll = pll = USMMCM(speedgrade=-2) - self.comb += pll.reset.eq(~main_pll.locked) + self.comb += pll.reset.eq(~main_pll.locked | self.rst) pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) @@ -144,7 +145,7 @@ def main(): args = parser.parse_args() soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer) - builder = Builder(soc, csr_csv="csr.csv") + builder = Builder(soc, output_dir="build/kcu105", csr_csv="csr.csv") builder.build(run=args.build) if args.load: diff --git a/bench/xcu1525.py b/bench/xcu1525.py index f7d616e..bc3166f 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -27,6 +27,7 @@ from litedram.phy import usddrphy class _CRG(Module, AutoCSR): def __init__(self, platform, sys_clk_freq, channel): + self.rst = Signal() self.clock_domains.cd_sys_pll = ClockDomain() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -44,7 +45,7 @@ class _CRG(Module, AutoCSR): main_pll.expose_drp() self.submodules.pll = pll = USPMMCM(speedgrade=-2) - self.comb += pll.reset.eq(~main_pll.locked) + self.comb += pll.reset.eq(~main_pll.locked | self.rst) pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)