diff --git a/litedram/core/refresher.py b/litedram/core/refresher.py
index f78ae05..24b5b77 100644
--- a/litedram/core/refresher.py
+++ b/litedram/core/refresher.py
@@ -8,7 +8,8 @@
 """LiteDRAM Refresher."""
 
 from migen import *
-from migen.genlib.misc import timeline
+
+from litex.gen.genlib.misc import timeline
 
 from litex.soc.interconnect import stream
 
diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py
index 70808ad..e1fb44a 100644
--- a/litedram/phy/ecp5ddrphy.py
+++ b/litedram/phy/ecp5ddrphy.py
@@ -14,10 +14,11 @@ from operator import or_
 import math
 
 from migen import *
-from migen.genlib.misc import timeline
+
 from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import timeline, WaitTimer
 
 from litex.soc.interconnect.csr import *
 
diff --git a/litedram/phy/gw2ddrphy.py b/litedram/phy/gw2ddrphy.py
index 39b1c31..9bb474a 100644
--- a/litedram/phy/gw2ddrphy.py
+++ b/litedram/phy/gw2ddrphy.py
@@ -15,10 +15,11 @@ from operator import or_
 import math
 
 from migen import *
-from migen.genlib.misc import timeline
+
 from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import WaitTimer
+
+from migen.genlib.misc import timeline, WaitTimer
 
 from litex.soc.interconnect.csr import *
 
diff --git a/litedram/phy/rpc/basephy.py b/litedram/phy/rpc/basephy.py
index 053646f..e324769 100644
--- a/litedram/phy/rpc/basephy.py
+++ b/litedram/phy/rpc/basephy.py
@@ -8,7 +8,8 @@ from math import ceil
 from operator import and_
 
 from migen import *
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
 
diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py
index 9a7ad43..80dc190 100644
--- a/litedram/phy/usddrphy.py
+++ b/litedram/phy/usddrphy.py
@@ -14,7 +14,8 @@ from operator import or_
 import math
 
 from migen import *
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect.csr import *
 
diff --git a/test/benchmark.py b/test/benchmark.py
index 08ec0bd..fd2f506 100755
--- a/test/benchmark.py
+++ b/test/benchmark.py
@@ -14,7 +14,8 @@ from functools import reduce
 from itertools import zip_longest
 
 from migen import *
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.build.sim.config import SimConfig