global: Switch to litex.gen.genlib.misc.

litedram/core/refresher.py

@@ -8,7 +8,8 @@
 """LiteDRAM Refresher."""
 
 from migen import *
-from migen.genlib.misc import timeline
+
+from litex.gen.genlib.misc import timeline
 
 from litex.soc.interconnect import stream
 

litedram/phy/ecp5ddrphy.py

@@ -14,10 +14,11 @@ from operator import or_
 import math
 
 from migen import *
-from migen.genlib.misc import timeline
+
 from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import timeline, WaitTimer
 
 from litex.soc.interconnect.csr import *
 

litedram/phy/gw2ddrphy.py

@@ -15,10 +15,11 @@ from operator import or_
 import math
 
 from migen import *
-from migen.genlib.misc import timeline
+
 from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import WaitTimer
+
+from migen.genlib.misc import timeline, WaitTimer
 
 from litex.soc.interconnect.csr import *
 

litedram/phy/rpc/basephy.py

@@ -8,7 +8,8 @@ from math import ceil
 from operator import and_
 
 from migen import *
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
 

litedram/phy/usddrphy.py

@@ -14,7 +14,8 @@ from operator import or_
 import math
 
 from migen import *
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect.csr import *
 

test/benchmark.py

@@ -14,7 +14,8 @@ from functools import reduce
 from itertools import zip_longest
 
 from migen import *
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.build.sim.config import SimConfig