From 62a31de21f7de0d5a75c11b22fc316909742f3f2 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 18 Dec 2018 11:24:38 +0100
Subject: [PATCH] phy: rename KUSDDRPHY to USDDRPHY since compatible with
 Kintex/Virtex Ultrascale

---
 README                                     | 2 +-
 litedram/phy/__init__.py                   | 2 +-
 litedram/phy/{kusddrphy.py => usddrphy.py} | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)
 rename litedram/phy/{kusddrphy.py => usddrphy.py} (99%)

diff --git a/README b/README
index 57ad39e..556fc6a 100644
--- a/README
+++ b/README
@@ -27,7 +27,7 @@ PHY:
   - Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice)
   - Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
   - Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
-  - Kintex Ultrascale DDR3/DDR4 PHY (1:4 frequency ratio)
+  - Kintex/Virtex Ultrascale DDR3/DDR4 PHY (1:4 frequency ratio)
 Core:
   - Fully pipelined, high performance.
   - Configurable commands depth on bankmachines.
diff --git a/litedram/phy/__init__.py b/litedram/phy/__init__.py
index 68703fa..b470f04 100644
--- a/litedram/phy/__init__.py
+++ b/litedram/phy/__init__.py
@@ -1,7 +1,7 @@
 from litedram.phy.gensdrphy import GENSDRPHY
 from litedram.phy.s6ddrphy import S6HalfRateDDRPHY, S6QuarterRateDDRPHY
 from litedram.phy.s7ddrphy import V7DDRPHY, K7DDRPHY, A7DDRPHY
-from litedram.phy.kusddrphy import KUSDDRPHY
+from litedram.phy.usddrphy import USDDRPHY
 
 # backward compatibility (remove when no longer needed)
 from litedram.phy import s7ddrphy as a7ddrphy
diff --git a/litedram/phy/kusddrphy.py b/litedram/phy/usddrphy.py
similarity index 99%
rename from litedram/phy/kusddrphy.py
rename to litedram/phy/usddrphy.py
index eedd101..a387f05 100644
--- a/litedram/phy/kusddrphy.py
+++ b/litedram/phy/usddrphy.py
@@ -1,4 +1,4 @@
-# 1:4 frequency-ratio DDR3/DDR4 PHY for Kintex Ultrascale
+# 1:4 frequency-ratio DDR3/DDR4 PHY for Kintex/Virtex Ultrascale
 # DDR3: 800, 1066, 1333 and 1600 MT/s
 # DDR4: 1600 MT/s
 
@@ -57,7 +57,7 @@ class DDR4DFIMux(Module):
             ]
 
 
-class KUSDDRPHY(Module, AutoCSR):
+class USDDRPHY(Module, AutoCSR):
     def __init__(self, pads, memtype="DDR3", sys_clk_freq=100e6):
         tck = 2/(2*4*sys_clk_freq)
         addressbits = len(pads.a)