From 63434324e6333f69a7ccb8cbcbe87e7b739158b7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Feb 2017 13:05:49 +0100 Subject: [PATCH] phy/kusddrphy: add TODO --- litedram/phy/kusddrphy.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/litedram/phy/kusddrphy.py b/litedram/phy/kusddrphy.py index 52a44bf..8cdd13e 100644 --- a/litedram/phy/kusddrphy.py +++ b/litedram/phy/kusddrphy.py @@ -9,6 +9,11 @@ from litedram.common import PhySettings from litedram.phy.dfi import * from litedram.phy.bitslip import BitSlip +# TODO: +# - verify read_latency in simulation (OSERDESE3/ISERDESE3) +# - verify initial p_DELAY_VALUE on ODELAYE3/IDELAYE3 +# - simulate with Micron's model +# - test on board class KUSDDRPHY(Module, AutoCSR): def __init__(self, pads): @@ -275,7 +280,7 @@ class KUSDDRPHY(Module, AutoCSR): # 2 cycles through OSERDESE3 TODO: verify latency # 2 cycles CAS # 2 cycles through ISERDESE3 TODO: verify latency - # 2 cycles through Bitslip + # 2 cycles through BitSlip rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en for i in range(8-1): n_rddata_en = Signal()